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Terrence Mak

Bio: Terrence Mak is an academic researcher from University of Southampton. The author has contributed to research in topics: Network on a chip & Power budget. The author has an hindex of 18, co-authored 143 publications receiving 1473 citations. Previous affiliations of Terrence Mak include Beihang University & Imperial College London.


Papers
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Journal ArticleDOI
12 Dec 2015-Sensors
TL;DR: This paper classifies the existing works into three categories as Static Sensor Network (SSN), Community Sensor network (CSN) and Vehicle sensor network (VSN) based on the carriers of the sensors.
Abstract: The air quality in urban areas is a major concern in modern cities due to significant impacts of air pollution on public health, global environment, and worldwide economy. Recent studies reveal the importance of micro-level pollution information, including human personal exposure and acute exposure to air pollutants. A real-time system with high spatio-temporal resolution is essential because of the limited data availability and non-scalability of conventional air pollution monitoring systems. Currently, researchers focus on the concept of The Next Generation Air Pollution Monitoring System (TNGAPMS) and have achieved significant breakthroughs by utilizing the advance sensing technologies, MicroElectroMechanical Systems (MEMS) and Wireless Sensor Network (WSN). However, there exist potential problems of these newly proposed systems, namely the lack of 3D data acquisition ability and the flexibility of the sensor network. In this paper, we classify the existing works into three categories as Static Sensor Network (SSN), Community Sensor Network (CSN) and Vehicle Sensor Network (VSN) based on the carriers of the sensors. Comprehensive reviews and comparisons among these three types of sensor networks were also performed. Last but not least, we discuss the limitations of the existing works and conclude the objectives that we want to achieve in future systems.

255 citations

Journal ArticleDOI
TL;DR: New interconnect technologies, such as optical interconnect, wireless NoC (WiNoC), RF transmission lines (RF-I) and surface wave interconnects (SWI), are discussed, evaluated and compared.
Abstract: Networks-on-chip (NoC) have emerged to tackle different on-chip communication challenges and can satisfy different demands in terms of performance, cost and reliability. Currently, interconnects based on metal are reaching performance limits given relentless technology scaling. In particular, a performance bottleneck has emerged due to the demands for communication in terms of bandwidth for multicasting and broadcasting. As a result, various state-of-the-art architectures have been proposed as alternatives and emerging interconnects including the use of optics or radio frequency (RF). This article presents a comprehensive survey of these various interconnect fabrics, and discusses their current and future potentials and obstacles as well. This article aims to drive the research community to achieve a better utilization of the merits of on-chip interconnects and addresses the challenges involved. New interconnect technologies, such as optical interconnect, wireless NoC (WiNoC), RF transmission lines (RF-I) and surface wave interconnects (SWI), are discussed, evaluated and compared. Consequently, these emerging interconnects can continue to provide the cost efficiency and performance that are highly demanded for future many-core processors and high performance computing.

112 citations

Journal ArticleDOI
TL;DR: A deadlock-free routing architecture which employs a dynamic programming (DP) network to provide on-the-fly optimal path planning and network monitoring for packet switching and a new routing strategy called k-step look ahead is introduced.
Abstract: Dynamic routing is desirable because of its substantial improvement in communication bandwidth and intelligent adaptation to faulty links and congested traffic. However, implementation of adaptive routing in a network-on-chip system is not trivial and is further complicated by the requirements of deadlock-free and real-time optimal decision making. In this paper, we present a deadlock-free routing architecture which employs a dynamic programming (DP) network to provide on-the-fly optimal path planning and network monitoring for packet switching. Also, a new routing strategy called k-step look ahead is introduced. This new strategy can substantially reduce the size of routing table and maintain a high quality of adaptation which leads to a scalable dynamic-routing solution with minimal hardware overhead. Our results, based on a cycle-accurate simulator, demonstrate the effectiveness of the DP network, which outperforms both the deterministic and adaptive-routing algorithms in average delay on various traffic scenarios by 22.3%. Moreover, the hardware overhead for DP network is insignificant, based on the results obtained from the hardware implementations.

82 citations

Journal ArticleDOI
TL;DR: A method that is capable of identifying critical pathways in a network at run-time and, then, can dynamically reconfigure the network to optimize for the network performance subjected to the identified dominated flows is introduced.
Abstract: Modern network-on-chip (NoC) systems are required to handle complex runtime traffic patterns and unprecedented applications. Data traffics of these applications are difficult to fully comprehend at design time so as to optimize the network design. However, it has been discovered that the majority of dataflows in a network are dominated by less than 10p of the specific pathways. In this article, we introduce a method that is capable of identifying critical pathways in a network at runtime and can then dynamically reconfigure the network to optimize for network performance subject to the identified dominated flows. An online learning and analysis scheme is employed to quickly discover the emerging dominated traffic flows and provides a statistical traffic prediction using regression analysis. The architecture of a self-tuning network is also discussed which can be reconfigured by setting up the identified point-to-point paths for the dominance dataflows in large traffic volumes. The merits of this new approach are experimentally demonstrated using comprehensive NoC simulations. Compared to the conventional network architectures over a range of realistic applications, the proposed self-tuning network approach can effectively reduce the latency and power consumption by as much as 25p and 24p, respectively. We also evaluated the configuration time and additional hardware cost. This new approach demonstrates the capability of an adaptive NoC to handle more complex and dynamic applications.

47 citations

Proceedings ArticleDOI
01 Aug 2006
TL;DR: Salient factors, which include quantitative performance metrics and qualitative factors, relevant to design are identified and used to analyze and classify the on-FPGA communication architectures.
Abstract: The recent development of Platform-FPGA or Field-Programmable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potential for immense computing power as well as opportunities for rapid system prototyping. These platforms require high-performance on-chip communication architectures for efficient and reliable inter-processor communication. However, as the number of embedded processors increases, communication bandwidth between embedded components becomes a limiting factor to overall system performance. In this paper, we survey the state-of-the-art on-FPGA communication architectures and methodologies. Salient factors, which include quantitative performance metrics and qualitative factors, relevant to design are identified and used to analyze and classify the on-FPGA communication architectures. This survey aims to facilitate innovation in and development of future on-FPGA communication architectures.

45 citations


Cited by
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01 Jan 2016
TL;DR: The table of integrals series and products is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can get it instantly.
Abstract: Thank you very much for downloading table of integrals series and products. Maybe you have knowledge that, people have look hundreds times for their chosen books like this table of integrals series and products, but end up in harmful downloads. Rather than reading a good book with a cup of coffee in the afternoon, instead they cope with some harmful virus inside their laptop. table of integrals series and products is available in our book collection an online access to it is set as public so you can get it instantly. Our book servers saves in multiple locations, allowing you to get the most less latency time to download any of our books like this one. Merely said, the table of integrals series and products is universally compatible with any devices to read.

4,085 citations

Journal ArticleDOI
TL;DR: The most common building blocks and techniques used to implement these circuits, and an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models.
Abstract: Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin-Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

1,559 citations

01 Jan 2016
TL;DR: The design of analog cmos integrated circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their chosen books like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they juggled with some harmful virus inside their computer. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library spans in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Kindly say, the design of analog cmos integrated circuits is universally compatible with any devices to read.

1,038 citations

01 Jan 2016
TL;DR: The design of analog cmos integrated circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you very much for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their favorite novels like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than reading a good book with a cup of coffee in the afternoon, instead they cope with some malicious virus inside their laptop. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library saves in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Merely said, the design of analog cmos integrated circuits is universally compatible with any devices to read.

912 citations