Showing papers by "Tetsu Tanaka published in 1994"

Ultrafast operation of V/sub th/-adjusted p/sup +/-n/sup +/ double-gate SOI MOSFET's

Abstract: To optimize the V/sub th/ of double-gate SOI MOSFET's, we fabricated devices with p/sup +/ poly-Si for the front-gate electrode and n/sup +/ poly-Si for the back-gate electrode on 40-nm-thick direct-bonded SOI wafers. We obtained an experimental V/sub th/ of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 /spl mu/m long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects. >

Analytical surface potential expression for thin-film double-gate SOI MOSFETs

Abstract: Using a perturbation theory, we derived an analytical surface potential expression for subthreshold and strong-inversion regions. This enabled us to derive analytical models for the subthreshold slope, threshold voltage, and induced electron concentration of a double-gate SOI MOSFET. We also clarified the dependence of the device characteristics on device parameters, and explained the ideal subthreshold factor. We do not expect volume inversion in practical devices. Our models' predictions agree well with numerical and experimental data.

Ultrafast low-power operation of p/sup +/-n/sup +/ double-gate SOI MOSFETs

Abstract: Using direct bonded SOI wafers just 40 nm thick, we fabricated p/sup +/-n/sup +/ double-gate SOI MOSFETs. These devices, with an appropriate Vth, have good short-channel behavior and a large drive current. For Lg=0.19 /spl mu/m, we obtained an inverter delay time of 43 ps at 1 V, and 27 ps at 2 V. These are the fastest reported values for this gate length. The high performance is attributed to the large drain current, the low series resistance, and the reduction of the parasitic drain junction capacitance. >

Source/drain contact resistance of silicided thin-film SOI MOSFET's

Abstract: We developed a source/drain contact (S/D) resistance model for silicided thin-film SOI MOSFET's, and analyzed its dependence on device parameters considering the variation in the thickness of the silicide and residual SOI layers due to silicidation. The S/D resistance is insensitive to the silicide thickness over a wide range of thicknesses; however, it increases significantly when the silicide thickness is less than one hundredth of initial SOI thickness, and when almost all the SOI layer is silicided. To obtain a low S/D resistance, the specific contact resistance must be reduced, that is, the doping concentration at the silicide-SOI interface must be more than 10/sup 20/ cm/sup -3/. >

Scaling Theory for Vth Controlled n+-p+ Double-Gate SOI MOSFETs

Abstract: materials to obtain a proper V.nttl. To alleviale the hurdle, we proposed an n+p* double-gate\\SoI MOSFET in which V,r, ir contnolled by ttre interaction between the front and back gates (Fig. l). Furthermore, we demonstrated a CMOS inverter delay of 27 ps for a device with I.o = 0.2 pm and b* = 9 nm at supply voltage Vof 2 V This device had a \\' of 0.25 V with an ideal S-swingt2l. We have established a scaling theory for the device and revealed the potential of how short channel region can this device go.