Showing papers by "Tetsu Tanaka published in 1998"
01 Dec 1998
TL;DR: In this paper, the impact of ultra-shallow junction and tilted channel implantation with respect to source/drain resistance (R/sub sd/), and short-channel effect (SCE) based on physical gate length and effective gate length (L/sub eff/) was discussed.
Abstract: The impact of ultra-shallow junction and tilted channel implantation (TCI) is discussed with respect to source/drain resistance (R/sub sd/), and short-channel effect (SCE) based on physical gate length (L/sub gate/) and effective gate length (L/sub eff/) We obtained the following results: (1) A shallower junction improves the SCE immunity for a given L/sub gate/, but not with respect to L/sub eff/ (2) The essential factor for the reduction of R/sub sd/ is not the sheet resistance (R/sub sheet/) of source/drain (S/D) extensions, but the junction tailing profile (3) TCI was found to be effective for increasing the current drive ability due to the reduced L/sub eff/ for a given off current (I/sub off/) (4) The effectiveness of TCI was confirmed by a CV L/sub eff/ extraction method (5) Encouraged by the above results, high-performance 01 /spl mu/m pMOSFETs were demonstrated using a 1 keV, B/sup +/ or BF/sub 2//sup +/ implantation and TCI technology The device achieved a high drive current (I/sub drive/) of 360 /spl mu/A//spl mu/m (@V/sub g/=V/sub d/=15 V, I/sub off/=1nA//spl mu/m)
14 citations
09 Jun 1998
TL;DR: In this paper, a 20-nm-thick counter-doped layer was used to suppress short-channel effects (SCE) in surface-channel PMOSFETs below the sub-0.25-μm technology range.
Abstract: Below the sub-0.25-/spl mu/m technology range, surface-channel (SC) PMOSFETs employing p+ poly-Si gates are widely used instead of buried-channel (BC) PMOSFETs employing n+ poly-Si gates. However, there are still many advantages of using an n+ poly-Si gate such as the absence of the undesirable Vth shift due to boron penetration through the gate oxide, no gate-dopant cross-diffusion, and process simplicity. The critical issues for extending the use of buried-channel PMOSFETs below the sub-0.25-/spl mu/m technology range, that is, the 4-Gbit DRAM era and beyond, are low Vth and also the suppression of short-channel effects (SCE), which can be achieved by an extremely shallow counter-doped layer with a high impurity concentration. Here, for the first time, we use decaborane (B/sub 10/H/sub 14/) ion implantation to fabricate a 20-nm-thick counter-doped layer and demonstrate an SCE-free high performance O.18-/spl mu/m BC-PMOSFET.
6 citations
06 Jan 1998
TL;DR: In this article, the authors propose a method to solve the problem of unstructured data.1.3.31 3.31 2.1 3.1 4.1
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