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Showing papers by "Tetsu Tanaka published in 2004"


Proceedings ArticleDOI
13 Dec 2004
TL;DR: In this paper, the operation principle and scalability of a capacitor-less 1T-DRAM are described and a new concept about extending the use of 1T DRAM to gate lengths of less than 50 nm is proposed.
Abstract: This paper describes both operation principle and scalability of a capacitor-less 1T-DRAM, and proposes a new concept about extending the use of 1T-DRAM to gate lengths of less than 50 nm. Superior characteristics such as long retention time and large sense margin even for gate lengths around 50 nm can be obtained with a double-gate fully depleted FinFET DRAM. Considering capacity, speed, power, and structural complexity of embedded memory, the capacitor-less 1T-DRAM has the possibility of playing the leading part among other memories.

165 citations


Patent
17 Nov 2004
TL;DR: In this paper, a radio repeater including at least first and second relay systems, each including a reception antenna configured to receive a radio signal, a loop interference suppressor, connected to the reception antenna, configured to suppress the loop interference signal in the received radio signal from said reception antenna.
Abstract: A radio repeater including at least first and second relay systems, each including a reception antenna configured to receive a radio signal, a loop interference suppressor, connected to the reception antenna, configured to suppress a loop interference signal in the received radio signal from said reception antenna, an amplifier configured to amplify the loop interference-suppressed radio signal from the loop interference suppressors, and a transmission antenna having a polarization characteristic, which is orthogonal to a polarization characteristic of said reception antenna, configured to transmit the output of said amplifier.

82 citations