Showing papers by "Tetsu Tanaka published in 2007"

New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique

Abstract: We have proposed a new three-dimensional (3D) integration technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D integration technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100%. As a result, we can obtain a high production yield even after bonding many wafers. In addition, it is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D integration technology based on the configured-wafer-on-wafer bonding technique (Reconfig. W-on-W 3D technology). We have developed key technologies to form W through-Si-Via (TSV) in the reconfigured wafer to fabricated 3D LSI test chips. We obtained excellent electrical characteristics of W-TSV using the daisy chain in 3D LSI test chip.

Memory cell array, method of producing the same, and semiconductor memory device using the same

Abstract: A memory cell array includes isolated semiconductor regions formed on a supporting insulating substrate, memory cells formed in the respective semiconductor regions, and insulating regions formed so as to insulate the memory cells. Each memory cell formed in a semiconductor region includes a source region, a drain region, a front gate region formed on a gate insulating film formed on one of side surfaces of the semiconductor region such that the source region and the drain region are separated from each other by the front gate region, and a back gate region formed on a gate insulating film formed on an opposite side surface of the semiconductor region such that the source region and the drain region are separated from each other by the back gate region. Each memory cell shares the back gate region with a memory cell adjacent in a row direction.

Self-Assembly Process for Chip-to-Wafer Three-Dimensional Integration

Abstract: We have proposed chip-to-wafer stacking for three-dimensional (3D) integration. To realize the chip-to-wafer 3D integration, five key technologies of through-Si interconnection and microbump formation, chip-to-wafer alignment, underfilling, and chip thinning were investigated. Three-layer stacked chips with a layer thickness of several tens microns were fabricated by using the key technologies. Each chip was serially and mechanically aligned and bonded onto a support LSI wafer. In addition, we newly introduce a stacking technique using self-assembly as a key process for advanced chip-to-wafer 3D integration. High-precision alignment with an accuracy of within 1 mum was obtained and stacking throughput can be dramatically improved by the self-assembly.

Fully Implantable Retinal Prosthesis Chip with Photodetector and Stimulus Current Generator

Abstract: To recover visual sensation of blind patients, we have fabricated a fully implantable retinal prosthesis chip that includes photodetector and stimulus current generator. For the first time, we successfully implanted the retinal prosthesis chip bonded on the flexible cable with stimulus electrode array into a rabbit eyeball. Moreover, we recorded and analyzed electrically evoked potential (EEP) elicited from a rabbit brain by current stimulation to retina.

Novel Optical/Electrical Printed Circuit Board with Polynorbornene Optical Waveguide

Abstract: An optical interconnection with a new optically transparent polymer called polynorbornene (PNB) was investigated for short-distance and high-speed data transmission on printed circuit boards (PCBs). PNB waveguides were formed by simple photoirradiation followed by heating without development and reactive ion etching (RIE) processes. The PNB waveguides exhibit a high-heat resistance of more than 270 °C and an extremely low optical loss of 0.029 dB/cm at 830 nm. We successfully integrated PNB waveguides into a multilayer PCB, which we call a optical/electrical printed circuit board (O/E-PCB), and confirmed a basic data transmission rate of 10 Gbps.

New magnetic nanodot memory with FePt nanodots

Abstract: A new magnetic nanodot (MND) memory with FePt nanodots was proposed. The FePt nanodots dispersed in SiO2 insulating film was successfully fabricated by self-assembled nanodot deposition (SAND). The size of the FePt nanodot can be controlled by SAND with a different target area ratio of the FePt pellets area in the SiO2 target. Thermal annealing converts the magnetic properties of the FePt nanodots from antiferromagnetic into high coercivity ferromagnetic without thermal agglomeration. An L10 face-centered tetragonal (fct) FePt MND film was successfully formed which acted as a charge retention layer. Furthermore, the fundamental characteristics of the MND memory were investigated using magnetic metal oxide semiconductor (MOS) capacitor devices.

Evaluation of Platinum-Black Stimulus Electrode Array for Electrical Stimulation of Retinal Cells in Retinal Prosthesis System

Abstract: A retinal prosthesis system with a three-dimensionally (3D) stacked LSI chip has been proposed. We fabricated a new implantable stimulus electrode array deposited with Platinum-black (Pt-b) on a polyimide-based flexible printed circuit (FPC) for the electrical stimulation of the retinal cells. Impedance measurement of the Pt-b electrode–electrolyte interface in a saline solution was performed and the Pt-b electrode realized a very low impedance. The power consumption at the electrode array when retinal cells were stimulated by a stimulus current was evaluated. The power consumption of the Pt-b stimulus electrode array was 91% lower than that of a previously fabricated Al stimulus electrode array due to a convexo-concave surface. In the cytotoxicity test (CT), we confirmed that Pt implantation induced no cellular degeneration of the rat retina. In the animal experiments, electrically evoked potential (EEP) was successfully recorded using Japanese white rabbits. These results indicate that electrical stimulation using the Pt-b stimulus electrode array can restore visual sensation.

High Performance Polynorbornene Optical Waveguide for Opto-Electric Interconnections

Abstract: We have newly developed a multi-mode polymer optical waveguide with polynorbornene (PNB). The PNB waveguide has extremely low optical loss of 0.03 dB/cm at wavelength of 830-nm and high glass transition temperature (Tg) of 270degC. The PNB waveguide can be formed by only UV irradiation step without both etching and developing processes. By using this method, the waveguide can be easily patterned with various shapes such as Y-branch, bend, taper, and so on. In addition, we can fabricate the minimum waveguide pitch less than 75 mum with the 50-mum-width core. We can also easily fabricate a stacked waveguide because the core layer with flat surface can be formed without an etching and a developing process. In the PNB waveguide, 45deg mirror was formed by an excimer laser. This method provides a small mirror (100 mum times 200 mum) with smooth surface in respective waveguides. From the result of insertion loss measurements, total optical loss was less than 2 dB in an 8-cm-length waveguide with two 45deg mirrors. Furthermore, new opto-electric (O-E) interconnection with PNB optical waveguide was proposed. This PNB waveguide has high flexibility and high adaptability to reflow soldering process because of its high Tg. Therefore, the PNB waveguide can be formed in flexible printed circuit boards (PCBs) without particular process, as compared to the conventional PCB fabrication process, which leads to low cost O-E interconnection.

New Reconfigurable Memory Architecture for Parallel Image Processing LSI with Three-Dimensional Structure

Abstract: A reconfigurable memory network for a parallel image-processing LSI with a three-dimensional structure is proposed. The proposed memory network can be dynamically configured by changing the connections between processing elements (PEs) and memories in accordance with the required part of the stored image data. In addition, a specification of the data bandwidth between PEs and the proposed memory network can be changed in the synchronization with single instruction stream-multiple data stream (SIMD) and multiple instruction stream-multiple data stream (MIMD) operations. Therefore, data transfer has greater flexibility. Also, from the result of the performance evaluation by implementation into the field programmable gate array (FPGA), it was successfully shown that the proposed memory network reduced the execution time by up to 28.2% for a 9×9 filtering operation.

A Passive Telemetry Interface System with Closed-loop Power Control Function for Body-implanted Applications

Abstract: In this paper, we propose a passive telemetry interface system for a body-implanted chip with a closed-loop power control function, which keeps the chip temperature at the allowable level for human body. The system is controlled by monitoring an excessive current at the implanted chip and limiting the power supply at the external interrogator unit. Power consumption of the current monitor circuit implemented in 0.18 mum standard CMOS technology is lower than 35 muW with a 1.8 V power supply. Experimental results of the closed-loop power control system confirm its expected features of a detecting current of 150 muA at a distance between the transponder and the interrogator less than 10 mm.

Continuous Scaling Methodology of Planar CMOS Transistors by Suppressing Fluctuation in Carrier Profile

Abstract: The effects of an amorphous Si gate on various electrical fluctuations were evaluated for aggressively scaled CMOS transistors. After developing an advanced amorphous Si gate stack that effectively suppressed gate depletion, we measured intra-wafer fluctuations in gate capacitance and threshold voltage (Vth). The amorphous Si gate decreased intra-wafer fluctuations, intrinsic fluctuations of the scaled transistors, asymmetric fluctuation of the threshold voltage, and fluctuation in threshold voltage mismatch between neighboring transistors in the SRAM. Based on these results, we estimated a yield of the scaled SRAM for 45 nm technology node.

Low power spin-transfer magnetoresistive random access memory writing scheme with selective word line bootstrap

Abstract: We describe a new writing scheme with a selective word line bootstrap for spin-transfer magnetoresistive random access memory (MRAM). Applying spin-transfer switching to MRAM, its writing power consumption decreases and its memory cell area is also reduced. However, during write operation, the required bit line cramp voltage for stored data switching depends on the value of stored data, magnetic tunnel junction (MTJ) characteristics, and switching current direction. Therefore, the bit line voltage must be optimized to minimize the power consumption. With the proposed scheme, word line voltage is varied according to the value of writing data in order to decrease the threshold bit line voltage. Furthermore, the spin-transfer MRAM resistance model with reading and writing operations was successfully implemented for the circuit simulation. From the simulation results, it was found that writing threshold bit line bias during writing operation can decrease from 17 to 28% with the proposed selective bootstrap. Also, more than 25% of the cell transistor gate width can be decreased. This result shows that the proposed writing scheme is effective in reducing power consumption, and can also reduce the MRAM cell area.

Memory Window Enhancement of MOS Memory Devices with High Density Self-Assembled Tungsten Nano-dot

Abstract: High Density Self-Assembled Tungsten Nano-dot Yanli Pei, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi 1 International Advanced Research and Education Organization, Tohoku University, 6-6-03 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8578, Japan 2 Dept. of Bioengineering and Robotics, Graduate School of Engineering, Tohoku University 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan Phone: +81-22-795-6906, E-mail: sdlab@sd.mech.tohoku.ac.jp

Magnetic characteristics of FePt nanodots formed by a self-assembled nanodot deposition method

Abstract: FePt nanodot with L10 face-centered-tetragonal (fct) structure has attracted considerable attention owing to its potentials for new applications including a high-density magnetic data storage and a novel nonvolatile memory which are produced by its high magnetocrystalline anisotropy. FePt nanodots dispersed in a SiO2 film (FePt nanodot film) were formed by a self-assembled nanodots deposition (SAND) method in which FePt and SiO2 are co-sputtered in a high-vacuum RF magnetron sputtering equipment. Furthermore, FePt nanodot film with a monolayer of FePt nanodots was formed by annealing at 800°C for 1 h, due to the agglomeration of FePt atoms diffused in SiO2 films. The electron holography was a powerful tool to study the single-domain FePt nanodots. In this study, not only the phenomenon of FePt diffusion was evaluated, but also the ferromagnetic phase of monolayer FePt nanodots was analysed by electron holography.