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Showing papers by "Tetsu Tanaka published in 2009"


Journal ArticleDOI
27 Feb 2009
TL;DR: The 3-D microprocessor test chip,3-D memorytest chip, 3- D image sensor chip, and 3-Ds artificial retina chip were successfully fabricated by using poly-Si TSV and tungsten (W/poly-Si) TSV technology.
Abstract: High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.

277 citations


01 Jan 2009
TL;DR: In this paper, a polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly poly-Si TSV for 3D integration was developed.
Abstract: High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chem- ical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.

261 citations


Proceedings ArticleDOI
19 Jan 2009
TL;DR: A three-dimensional integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs and a new reconfigurable parallel image processing system is proposed.
Abstract: A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing system. To achieve this system, we have proposed a new 3-D integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration.

84 citations


Proceedings ArticleDOI
01 Dec 2009
TL;DR: In this article, Li et al. demonstrate two types of 3D integration using chip self-assembly techniques with liquid surface tension, in which many different sizes of chips having In/Au microbumps with/without TSV (through-silicon via) were temporarily placed on a reconfigured wafer in a back-to-face manner.
Abstract: We demonstrate two types of three-dimensional (3D) integration using chip self-assembly techniques with liquid surface tension. In reconfigured wafer-to-wafer 3D integration, many different sizes of chips having In/Au microbumps with/without TSV (through-silicon via) were temporarily placed by self-assembly on a reconfigured wafer in a back-to-face manner. The many chips can be then simultaneously transferred to an LSI wafer that is fully faced with the reconfigured wafer and has the same microbump array patterns to the self-assembled chips. On the other hand, in multichip-to-wafer 3D integration, Si chips having In/Au microbumps with sizes of 5 µm and 10 µm were directly self-assembled on another LSI wafer having the same In/Au microbumps in a face-to-face manner. After the self-assembly, these chips can be bonded at 200 °C without applying mechanical pressure. In both of the self-assembly-based 3D integration, the chips were precisely aligned and bonded to the LSI wafers through the microbump-to-microbump interconnection. We obtained good electrical characteristics using the microbump daisy chains formed between the self-assembled chips and the wafers.

50 citations


Proceedings ArticleDOI
30 Oct 2009
TL;DR: Novel micro-bumping technology to realize small size, fine pitch and uniform height Cu/ Sn bumps is developed and CMOS compatible dry etching processes for removing sputtered Cu/Ta layers are developed to achieve small size and fine pitch Cu/Sn bump.
Abstract: We develop novel micro-bumping technology to realize small size, fine pitch and uniform height Cu/Sn bumps. Electroplated-evaporation bumping (EEB) technology, which is a combination of Cu electroplating and Sn evaporation, is developed to achieve uniform height of Cu/Sn bumps. We develop CMOS compatible dry etching processes for removing sputtered Cu/Ta layers to achieve small size and fine pitch Cu/Sn bump. 5 µm square and 10 µm pitch Cu/Sn micro-bumps are successfully fabricated for the first time. Bump height variation is 5 µm ±3 % (95%, 2σ), which is uniform compared to electroplated Cu/Sn bumps. We evaluate micro-joining characteristics of Cu/Sn micro-bumps. Good I–V characteristics are measured from the daisy chain consisting of 1500 bumps with 10 µm square and 20 µm pitch. Resistance of Cu/Sn bump is 35 mΩ/bump, which is very low value compared to electroplated Cu/Sn bumps.

47 citations


Proceedings ArticleDOI
01 Dec 2009
TL;DR: In this paper, a 3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS) was proposed by integrating LSI, passives, MEMS and optoelectronic devices.
Abstract: We proposed 3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS). In order to realize 3D opto-electronic integrated system-on-silicon (SOS), we developed novel heterogeneous integration technology of LSI, MEMS and optoelectronic devices by implementing 3D heterogeneous opto-electronic multi-chip module composed with LSI, passives, MEMS and optoelectronic devices. The electrical interposer mounted with amplitude shift keying (ASK) LSI, LC filter and pressure-sensing MEMS chips and the optical interposer embedded with vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) chips are precisely bonded to form 3D opto-electronic multi-chip module. Opto-electronic devices are electrically connected via through-silicon vias (TSVs) which were formed into the interposers. Micro-fluidic channels are formed into the interposer by wafer direct bonding technique. 3D heterogeneous opto-electronic multi-chip module is successfully implemented for the first time.

45 citations


Proceedings ArticleDOI
01 Dec 2009
TL;DR: In this paper, the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated by micro-Raman spectroscopy (µRS) and XPS.
Abstract: Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated. The remnant stress left after wafer thinning was evaluated by micro-Raman spectroscopy (µRS) and XPS. It was found that the mechanical stress remained in the back surface of Si substrate after wafer thinning and a part of this mechanical stress appeared in the surface of Si substrate. The metal contamination in such thinned Si substrate has been evaluated by a C-t method. It was found that the carrier generation lifetime was degraded by Cu diffused into Si substrate at relatively low temperature of 200 °C. The mechanical stress/strain in the thinned Si substrate after wafer bonding was also evaluated to investigate the influences of metal microbumps to the thinned Si substrate. It was found that the local mechanical stress was generated in the Si substrate surface by the microbumps. This local stress caused a 3% change in the ON current of MOS transistor.

39 citations


Journal ArticleDOI
TL;DR: In this paper, the microwave oscillations due to a spin transfer effect induced by direct current in ferromagnetic nanocontact magnetoresistive (NCMR) elements with a current-perpendicular-to-plane spin-valve structure were investigated.
Abstract: We have investigated the microwave oscillations due to a spin transfer effect induced by direct current in ferromagnetic nanocontact magnetoresistive (NCMR) elements with a current-perpendicular-to-plane spin-valve structure consisting of an FeCo/FeCo–AlOx nano-oxide layer/FeCo multilayer for the reference/spacer/free layers, respectively. Characteristic microwave oscillations were observed in the NCMR elements at different magnetization states induced by the application of a spin-polarized current, which are considered to be related to the introduction of a ferromagnetic NC to spacer layer (large interlayer coupling) and the resonance concerning the stability of the magnetization states of the free and reference layers around the NCs. A marvelously narrow full width at half maximum (FWHM) of l0–20 MHz is observed under a high applied magnetic field where the reference layer magnetization is slightly off axis relative to the pinned direction. By contrast, a wider FWHM of 80–600 MHz is observed at the magn...

26 citations


Journal ArticleDOI
TL;DR: In this paper, high resolution transmission electron microscopy and x-ray photoelectron spectroscopy analyses clearly show that the high metallic Co-ND is crystallized with small size of ∼2nm and high density of (4-5)×1012/cm2.
Abstract: In this letter, cobalt nanodots (Co-NDs) had been formed via a self-assembled nanodot deposition. High resolution transmission electron microscopy and x-ray photoelectron spectroscopy analyses clearly show that the high metallic Co-ND is crystallized with small size of ∼2 nm and high density of (4–5)×1012/cm2. The metal-oxide-semiconductor device with high density Co-NDs floating gate and high-k HfO2 blocking dielectric exhibits a wide range memory window (0–12 V) due to the charge trapping into and distrapping from Co-NDs. After 10 years retention, a large memory window of ∼1.3 V with a low charge loss of ∼47% was extrapolated. The relative longer data retention demonstrates the advantage of Co-NDs for nonvolatile memory application.

22 citations


Proceedings ArticleDOI
30 Oct 2009
TL;DR: To recover visual sensation of blind patients, a novel three dimensionally stacked retinal prosthesis chip in which several LSI chips such as consisting of photodetector, signal processing circuit and stimulus current generator are vertically stacked and electrically connected using 3D integration technology is proposed.
Abstract: To recover visual sensation of blind patients, we have proposed a novel three dimensionally (3D) stacked retinal prosthesis chip in which several LSI chips such as consisting of photodetector, signal processing circuit and stimulus current generator are vertically stacked and electrically connected using 3D integration technology. In this work, we developed several key process for realizing 3D stacked retinal prosthesis chip. Fine sized Cu TSV of 10 µm width and 30 µm depth was successfully formed from the back side of the thinned prosthesis chip. The prosthesis chip with the back side Cu TSVs was flip-chip bonded to Si substrate/flexible substrate through Cu/Sn micro-bumps for evaluating the feasibility of 3D integration technology.

21 citations


Proceedings ArticleDOI
30 Oct 2009
TL;DR: The fundamental study of a parallel signal processing circuit, which includes a pixel circuit and a parallel analog-to-digital converter (ADC) with hierarchical correlated double sampling (CDS), with block-parallel signal processing with three-dimensional (3D) structure is described.
Abstract: In this paper, we describe the fundamental study of a parallel signal processing circuit, which includes a pixel circuit and a parallel analog-to-digital converter (ADC) with hierarchical correlated double sampling (CDS). To realize high speed image capturing sensor, we have proposed a block-parallel signal processing with three-dimensional (3D) structure. Using 3D structure, the different function layers are stacked vertically and interconnected electrically by through-Si vias (TSVs), which can improve sensor performance and signal band width. On the other hand, the fixed pattern noise (FPN), caused by the circuit device variation, becomes a critical challenge. Experiments on the fabricated pixel circuit have been implemented in a single-layer (two-dimensional) 0.18-µm CMOS image sensor technology. With the analog CDS, the FPN of pixel circuit is reduced by 8.6%. To eliminate the FPN of parallel ADC, a digital CDS technique is implemented. The proposed ADC with digital CDS is designed in a two-dimensional 0.18-µm CMOS technology. The ADC design, including an 8-bit memory, a 6-bit memory, a subtraction circuit, and a comparator, occupies 100×100µm2 area and 0.9mW with supply voltage 1.8 V and 1 MS/s conversion rate. The functional simulation and measurement results confirm that our techniques can effectively reduce fixed pattern noise.

Proceedings ArticleDOI
26 May 2009
TL;DR: In this paper, a very new interconnection method, namely Cu lateral interconnection is proposed and tested for the heterogeneous multi-chip module integration in which MEMS and LSI chips are self assembled onto the flexible substrate.
Abstract: A very new interconnection method, namely Cu lateral interconnection is proposed and tested for the heterogeneous multi-chip module integration in which MEMS and LSI chips are self assembled onto the flexible substrate. Here, the lateral interconnects runs between a few hundred microns thick chip and the Si or flexible substrates as well as at inter chip level. These Cu lateral interconnects were fabricated via conventional electroplating technique. As formed single as well as daisy chain lateral interconnects (both are crossing over the thick test chips that are face-up bonded onto the flexible substrates by self-assembly) were characterized for their electrical characteristics. We have obtained a low resistance values for the Cu lateral interconnects which are close to the calculated values. Further, a module contains RF test chips that are interconnected by this unique Cu lateral interconnections has been tested for the operation.

Journal ArticleDOI
TL;DR: In this article, the formation of high density tungsten nanodots (W-NDs) embedded in silicon nitride via a self-assembled nanodot deposition is demonstrated.
Abstract: In this letter, the formation of high density tungsten nanodots (W-NDs) embedded in silicon nitride via a self-assembled nanodot deposition is demonstrated. In this method, tungsten and silicon nitride are cosputtered in high vacuum rf sputtering equipment. The W-NDs with small diameters (1–1.5 nm) and high density (∼1.3×1013/cm2) were achieved easily by controlling W composition; this is the ratio of total area of W chips to that of silicon nitride target. The metal-oxide-semiconductor memory device was fabricated with high density W-NDs floating gate and high-k HfO2 blocking dielectric. A wide range memory window (0–29 V) was obtained after bidirectional gate voltages sweeping with range of ±1–±23 V. It is feasible to design the memory window with propriety power consumption for nonvolatile memory application.

Journal ArticleDOI
TL;DR: A novel Si double-sided microelectrode that has recording sites on both front and back sides is proposed and successfully recorded neuronal action potentials from the recording sites of both sides.
Abstract: We have proposed a new implantable neural recording system, which we call the brain signal processing system (BSPS). In this system, LSI chips such as amplifiers, analog-to-digital converters, and multiplexers are integrated on the Si microelectrode array. To analyze the brain functions or to develop medical treatments for brain disorders, a high-density recording of action potentials is strongly required. To realize high-density recording of action potentials, we propose a novel Si double-sided microelectrode that has recording sites on both front and back sides. The back-side recording sites are connected to a recording apparatus by wire bonding through Si via holes. We fabricated the carefully designed Si double-sided microelectrode and evaluated the electrical characteristics of the Si microelectrode. The front- and back-side recording sites had impedance values of 2.5 and 2.7 MΩ at 1 kHz, respectively, which indicated that both recording sites have equivalent characteristics. An in vitro experiment of neuronal action potential recording using the fabricated Si double-sided microelectrode was performed. The CA1 areas of 400-µm-thick hippocampal slices obtained from the brains of guinea pigs were employed, and we successfully recorded neuronal action potentials from the recording sites of both sides.

Journal ArticleDOI
TL;DR: In this paper, a Si neural probe with a microfluidic channel to deliver drugs into neural tissue was presented. But the Si probe had sufficient bonding strength to eject liquid.
Abstract: This paper reports the development of a novel Si neural probe with a microfluidic channel to deliver drugs into neural tissue. We fabricated this Si neural probe using wafer direct bonding. To confirm the fluidic capability of the fabricated Si probe, we demonstrated the ejection of liquid from the microfluidic channel using a syringe pump. We confirmed that the Si probe had sufficient bonding strength to eject liquid. In addition, we investigated the pressure drops in the microfluidic channel. From the results, we observed a linear relationship between the flow rate and the pressure drop. Since this result agreed well with the calculated values, we confirmed that the microfluidic channel was successfully formed by wafer direct bonding.

Journal ArticleDOI
TL;DR: In this article, a multiple alloy metal nano-dots memory using Fowler-Nordheim (FN) tunneling was investigated in order to confirm its structural possibility for future flash memory.
Abstract: A multiple alloy metal nano-dots memory using FN tunneling was investigated in order to confirm its structural possibility for future flash memory. In this work, a multiple FePt nano-dots device with a high work function (~5.2 eV) and extremely high dot density (~1.2 × 1013 cm−2) was fabricated. Its structural effect for multiple layers was evaluated and compared to the one with a single layer in terms of the cell characteristics and reliability. We confirm that MOS capacitor structures with two to four multiple FePt nano-dot layers provide a larger threshold voltage window and better retention characteristics. Furthermore, it was also revealed that several process parameters for block oxide and inter-tunnel oxide between the nano-dot layers are very important to improve the efficiency of electron injection into multiple nano-dots. From these results, it is expected that a multiple FePt nano-dots memory using Fowler–Nordheim (FN) tunneling could be a candidate structure for future flash memory.

Proceedings ArticleDOI
01 Dec 2009
TL;DR: In this article, the dependence of temperature uniformity dufing millisecond annealing (MSA) on the pattern density and its effect on device characteristics and static random access memory (SRAM) yields with 45-nm node technology was investigated.
Abstract: We investigated the dependence of temperature uniformity dufing millisecond annealing (MSA) on the pattern density and its effect on device characteristics and static random access memory (SRAM) yields with 45-nm node technology. By comparing flash lamp annealing (FLA) and laser spike annealing (LSA), we found FLA was difficult to use in our multiple MSA scheme without absorbing layers because of its high temperature uniformity sensitivity to pattern density. LSA was found to be more promising due to its lower sensitivity to pattern density and higher potential for enhancing performance. We also found hot spots were generated during LSA; however, these can easily be avoided by introducing LSA-friendly design rules.

Journal ArticleDOI
TL;DR: A fundamental study of a complementary metal oxide semiconductor (CMOS) image sensor for a three-dimensional (3D) image-processing system and a pixel circuit with correlated double sampling (CDS) and high-speed image capturing for high- speed image processing is proposed.
Abstract: In this paper, we describe a fundamental study of a complementary metal oxide semiconductor (CMOS) image sensor for a three-dimensional (3D) image-processing system. We proposed a pixel circuit with correlated double sampling (CDS) and high-speed image capturing for high-speed image processing. The CDS and high-speed image-capture circuit should be realized simultaneously to allow high-speed image processing. The pixel circuit can realize CDS and high-speed image-capture functions simultaneously. The CDS and high-speed image capturing are realized by using a pixel sample hold capacitor and shared coupling capacitor. Appending extra capacitors causes the pixel circuit size to become large in the two-dimensional (2D) CMOS image sensor. We proposed a 3D CMOS image sensor that can reduce the pixel circuit size and the electrical wiring length and increase the fill factor, even with CDS and high-speed image capturing. Therefore, small, high-speed parallel-processing systems can be realized by using our 3D CMOS image sensor. We fabricated the prototype 2D pixel circuit with CDS and high-speed image capturing. The prototype pixel circuit is successfully implemented in the simultaneous function. We believe the proposed pixel circuit is very effective for 3D CMOS image processing.

Proceedings ArticleDOI
23 Jun 2009
TL;DR: A newly developed holder designed to make a micro-perforation through the dura matter in which a silicon electrode can easily be inserted is described.
Abstract: Micro-machined silicon microelectrodes are useful for obtaining high-density, high-spatial resolution sampling of neuronal activity within the brain, and hold promise for revealing the spatiotemporal dynamics of local circuits. However, the fragile nature of silicon electrodes precludes their application in chronic recordings for a long period of time in which electrodes are repeatedly passed through the hardened dura matter. Here, we describe a newly developed holder designed to make a micro-perforation through the dura matter in which a silicon electrode can easily be inserted.

Proceedings ArticleDOI
23 Jun 2009
TL;DR: The development of a novelSi neural probe with microfluidic channels which is the key part of the intelligent Si neural probe system which can realize high density and multifunctional recording of neuronal behaviors is reported.
Abstract: We have proposed the intelligent Si neural probe system which can realize high density and multifunctional recording of neuronal behaviors. In this device, LSI chips such as amplifiers, A/D converters, and multiplexers are integrated on the intelligent Si neural probe. In this paper, we report the development of a novel Si neural probe with microfluidic channels which is the key part of the intelligent Si neural probe system. The Si neural probe has microfluidic channels fabricated using a wafer bonding technique to deliver drugs into the brain when neuronal action potentials are recorded. Furthermore, our Si neural probe has recording sites on both front- and back-side of Si to realize high density recording. We fabricated the carefully-designed Si neural probe, and evaluated characteristics of microfluidic channels. From the liquid ejection test, we confirmed that there was no void at bonding interfaces. We observed the liner relationship between the flow rate and the pressure drop, and the relationship was identical to that from the calculation, which indicated that the microfluidic channel was successfully formed. In addition, we fabricated the Si neural probe for in vivo neural recording. Both front- and back-side recording sites of the fabricated Si neural probe had impedance values of 1.5 MΩ and 1.2 MΩ at 1 kHz, respectively, which indicated that both recording sites had equivalent characteristics. The neuronal action potentials in motor area of Japanese macaque's brain were successfully recorded by using the fabricated Si neural probe.

Journal ArticleDOI
TL;DR: In this paper, the current induced magnetization dynamics, so called spin torque oscillation, in magnetic nano-contact MR element with a synthetic antiferromagnetic type spin-valve structure under high in-plane applied magnetic field of 0.9-1 kOe was investigated.
Abstract: We investigated the current induced magnetization dynamics, so called spin torque oscillation, in magnetic nano-contact MR element with a synthetic antiferromagnetic type spin-valve structure under high in-plane applied magnetic field of 0.9-1 kOe. Very high level oscillation of 18 nVHz-1/2 with narrow FWHM of 12 MHz was observed in the condition of negative applied current where electron-spin is injected from free layer to reference one. Applied current dependency on an oscillation frequency is a blueshift with good linearlity, and same dependency on level and FWHM is almost constant in the range of -10 to -14 mA, while applied field dependency on frequency shows redshift with two different slopes, -2.5 MHz/Oe in less than 1 kOe and -8.7 MHz/Oe in more than 1 kOe which field is smaller than the spin-flop field for the synthetic antiferromagnet, besides very clear and reasonable peak and bottom for oscillation level and FWHM are observed, respectively. It is thought that these magnetization dynamics are originated from synthetic antiferromagnet.

Proceedings ArticleDOI
30 Oct 2009
TL;DR: Fundamental characteristics were successfully obtained from pressure sensing MEMS chip with 360µm thickness, which was connected to the substrate by the cavity chip, which can give strong solution for heterogeneous integration of MEMS and LSI chips multi-chip module.
Abstract: We developed novel interconnection technology for heterogeneous integration of MEMS and LSI multi-chip module, in which MEMS and LSI chips would be horizontally integrated on substrate and vertically stacked each others. The cavity chip composed of deep Cu TSV-beam lead wires was developed for interconnecting MEMS chips with high step height of more than 100um. Fundamental characteristics were successfully obtained from pressure sensing MEMS chip with 360µm thickness, which was connected to the substrate by the cavity chip. MEMS and LSI chips were vertically integrated by using the cavity chip without changes of chip design and extra processes. This interconnection technology can give strong solution for heterogeneous integration of MEMS and LSI chips multi-chip module.


Proceedings ArticleDOI
30 Oct 2009
TL;DR: Mechanical stress, crystal defects, and metal contamination in thinned silicon substrates with and without intrinsic gettering (IG) zone have been investigated for three-dimensional (3D) integration.
Abstract: Mechanical stress, crystal defects, and metal contamination in thinned silicon substrates with and without intrinsic gettering (IG) zone have been investigated for three-dimensional (3D) integration The remnant stress existing after wafer thinning was evaluated using angle-(5°) polished silicon wafers by micro-Raman spectroscopy (μRS) The metal contamination in the thinned silicon substrates has been evaluated by a capacitance - time (C-t) measurement method using MOS capacitors in which the thinned silicon substrates were diffused with metallic impurities such as Cu and Au used for through-silicon via (TSV) and metal micro-bump in 3D LSI

Journal ArticleDOI
TL;DR: In this article, the use of CoCrW seed layer (SL) for making the fine grain granular structure and high crystalline orientation of the CoCrPt-oxide magnetic recording layer was reported.
Abstract: We report the use of CoCrW seed layer (SL) for making the fine grain granular structure and high crystalline orientation of CoCrPt-oxide magnetic recording layer. It is found that CoCrW SL should be of amorphouslike structure to make fine grain of CoCrPt-oxide magnetic layer. Moreover, the smooth surface of CoCrW SL provides high crystalline orientation of the CoCrPt-oxide magnetic layer.

Journal ArticleDOI
TL;DR: In this article, a novel optical interposer with optical interconnections is proposed for integrating three-dimensional (3D) LSI chips on this interposers, which realize precise passive alignment between the optical waveguides and the VCSEL/PD chips using two-step alignment processes consisting of cavity-assisted positioning and subsequent surface-tension-powered self-assembly with a molten solder.
Abstract: A novel optical interposer with optical interconnections is proposed for integrating three-dimensional (3D) LSI chips on this interposer. Vertical-cavity surface-emitting laser diode (VCSEL) chips and photo diode (PD) chips are buried in the optical interposer with polymeric optical waveguides. The VCSEL is 0.25 mm in width, 0.35 mm in length, and 0.15 mm in height. We realize precise passive alignment between the optical waveguides and the VCSEL/PD chips using two-step alignment processes consisting of cavity-assisted positioning and the subsequent surface-tension-powered self-assembly with a molten solder. In addition, we demonstrate the basic operation of the buried VCSEL chips in the optical interposer through tapered through-silicon vias (TSVs). The tapered TSVs are successfully formed by copper electroplating and are 64 µm in top width, 34 µm in bottom width, and 168 µm in length.

Journal ArticleDOI
TL;DR: A simple and inexpensive method to insert structurally weak electrodes into the brain through the thickened dura mater, which provides greater degree of freedom regarding the shape and the placement of electrodes compared to the conventional guide tube systems.

Proceedings ArticleDOI
30 Oct 2009
TL;DR: A new self-assembled die bonder to produce three-dimensionally integrated circuit (3D IC) using a multichip-to-wafer bonding method in batch and the average alignment accuracy was found to be approximately 400 nm and the total alignment time was less than 0.1 sec.
Abstract: We developed a new self-assembled die bonder to produce three-dimensionally integrated circuit (3D IC) using a multichip-to-wafer bonding method in batch. In the self-assembled multichip bonder, large number of known good dies (KGDs) can be simultaneously transferred to an LSI wafer on which hydrophilic bonding areas with liquid droplets are prepared. The many KGD can be aligned to the bonding areas by the liquid surface tension. The average alignment accuracy was found to be approximately 400 nm and the total alignment time was less than 0.1 sec. After liquid evaporation, the many KGDs can be bonded to the bonding areas in the new self-assembled die bonder.

Book ChapterDOI
01 Dec 2009
TL;DR: The development of a novel multichannel Si neural microelectrode with microfluidic channels which is the key part of the intelligent Si neural probe, which successfully recorded neuronal action potentials from CA1 area in a hippocampal slice.
Abstract: We have proposed the intelligent Si neural probe which can realize high density and multifunctional recording of neuronal behaviors. In this device, LSI chips such as amplifiers, A/D converters, and multiplexers are integrated on the Si neural probe. In this paper, we report the development of a novel multichannel Si neural microelectrode with microfluidic channels which is the key part of the intelligent Si neural probe. The microelectrode has microfluidic channels fabricated using a wafer bonding technology to deliver drugs into the brain when neuronal action potentials are recorded. And also, our microelectrode has recording sites on both front- and backside of Si to realize high density recording. We fabricated the carefully-designed multichannel Si neural microelectrode, and we evaluated characteristics of both recording sites and microfluidic channels. From the liquid ejection test, we confirmed that there was no void at bonding faces. We observed the liner relationship between the flow rate and the pressure drop, and the relationship was identical to that from the calculation, which indicated that the microfluidic channel was successfully formed. Moreover, both front- and back-side recording sites had impedance values of 2.5 M∖ and 2.7 M∖ at 1 kHz, respectively, which indicated that both recording sites had equivalent characteristics. The neuronal action potentials from CA1 area in a hippocampal slice were successfully recorded by using the fabricated microelectrode.