Showing papers by "Tetsu Tanaka published in 2011"

Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems

Abstract: We have developed a new 3-D hybrid integration technology of complementary metal-oxide-semiconductors, microelectromechanical systems (MEMS), and photonics circuits for optoelectronic heterogeneous integrated systems. We have overcome the fabrication difficulties of optoelectromechanical and microfluidics hybrid integration. In order to verify the applied 3-D hybrid integration technology, we fabricated a 3-D optoelectronic multichip module composed of large-scale integration (LSI), MEMS, and photonics devices. The electrical chips of amplitude-shift keying (ASK) LSI, passive, and pressure-sensing MEMS were mounted onto an electrical Si interposer with through-silicon vias (TSVs) and microfluidic channels. Photonics chips of vertical-cavity surface-emitting lasers and photodiodes were embedded into an optical Si interposer with TSVs. The electrical and optical interposers were precisely bonded together to form a 3-D optoelectronic multichip module. The photonics and electrical devices could communicate via TSVs. The photonics devices could be connected via an optical waveguide formed onto the optical interposer. Microfluidic channels were formed into the interposer by a wafer-direct bonding technique for heat sinking from high-power LSIs. In this paper, we evaluated the basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the 3-D optoelectronic multichip module to verify the applied 3-D hybrid integration technology. LSI, passive, MEMS, and photonics devices were successfully implemented. The 3-D hybrid integration technology is capable of providing a powerful solution for realizing optoelectronic heterogeneous integrated systems.

Evaluation of Cu Diffusion From Cu Through-Silicon Via (TSV) in Three-Dimensional LSI by Transient Capacitance Measurement

Abstract: The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI has been electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10- and 100-nm thicknesses (at the surface) were fabricated. The C-t curves of the trench capacitors with 100-nm-thick Ta layer exhibit no change after annealing up to 60 min at 300 °C. However, the C-t curves of the trench capacitors with 10-nm-thick Ta layer were severely degraded even after the initial annealing for 5 min. It means that Cu atoms diffuse into the active area from the Cu TSV through scallop portions with extremely thin Ta layer in TSVs, and consequently, the generation lifetime of minority carrier is significantly reduced. The C-t analysis is a useful method to electrically characterize the influence of Cu contamination from the Cu TSV on device reliability in fabricated LSI wafers.

Multichip Self-Assembly Technology for Advanced Die-to-Wafer 3-D Integration to Precisely Align Known Good Dies in Batch Processing

Abstract: An advanced die-to-wafer 3-D integration using a surface-tension-driven multichip self-assembly technology was proposed to 3-D stack a large number of known good dies (KGDs) in batch processing. The parallel self-assembly with a unique multichip pick-up tool was newly applied to die-to-wafer 3-D integration to overcome throughput and yield problems in conventional 3-D integration approaches. In addition, novel batch transfer of chips self-assembled on a carrier wafer to the corresponding target wafer was demonstrated. By using the multichip self-assembly, many KGDs can be precisely aligned and temporarily placed on a carrier wafer all at once, and then, the self-assembled KGDs can be simultaneously transferred to another target wafer in a face-to-face bonding manner at the wafer level. Average alignment accuracy was found to be approximately 400 nm when a hundred 3-mm-square chips were self-assembled on carrier wafers with small droplets of an aqueous solution. The alignment accuracy was experimentally proven to be fairly dependent on liquid surface tension as a self-assembly parameter. The liquid wettability contrast between the chip assembly areas and the surrounding areas formed on carrier wafers was another key parameter for alignment accuracy. The former and the latter areas were rendered high hydrophilic and hydrophobic. These areas, respectively, showed water contact angles less than 5° and 115°. Therefore, various sizes of chips (3 × 3 mm, 5 × 5 mm, 4 × 9 mm, and 10 × 10 mm) were self-assembled on a carrier wafer with high alignment accuracy, and further, the self-assembled chips were successfully transferred to the other faced target wafer in a batch.

High density 3D LSI technology using W/Cu hybrid TSVs

Abstract: High density 3D LSI technology using W/Cu hybrid through silicon vias (TSVs) has been proposed. Major reliability issues attributed to W/Cu hybrid TSVs in high density 3D LSIs such as (i) thermo-mechanical stress exerted by W TSVs used for signal lines and Cu TSVs used for power/ground lines in active Si, (ii) external gettering (EG) role played by sub-surface defects in thinned Si substrate, and (iii) effect of local stress induced by μ-bumps on device characteristics are discussed. By annealing at the temperature of ≥300°C, both Cu (via size ≤10µm) and W (via size ≤1µm) square TSVs induce only compressive stress at small TSV spacing which will seriously affect the mobility in active Si area, and thus device characteristics. Large compressive stress not only leads to extrusion and peeling of TSV metal, but also die cracking, and it will adversely impact on the reliability of 3D-LSIs. Then it was proposed to increase the TSV pitch to larger than twice of TSV size to avoid these adverse effects in high density 3D-LSI. Sub-surface defects at dry polished (DP) surface well act as potential EG sites for Cu contamination. Influences of mechanical stress induced by μ-bumps on device characteristics were also evaluated and ultra-small size In-Au μ-bump technology has been developed to minimize the influences of μ-bumps on device characteristics.

Evaluation of Cu Contamination at Backside Surface of Thinned Wafer in 3-D Integration by Transient-Capacitance Measurement

Abstract: The influence of Cu contamination at backside surface of a thinned wafer in three-dimensional LSI was electrically evaluated by capacitance-time (C-t) measurement. A MOS capacitor was fabricated using a thinned wafer of 50-μm thickness. The (C-t) curves of the MOS capacitor were severely degraded even after initial annealing at 300 °C for 5 min. It means that Cu atoms at the back surface reach the Si-SiO2 interface of the front surface, and the generation lifetime is significantly reduced. The quantitative relationship between the generation lifetime and surface concentration of Cu atom was evaluated. The (C-t) measurement is a highly promising method to electrically characterize the influence of Cu contamination on device reliability in fabricated LSI wafers.

Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration

Abstract: New surface mounting and packaging technologies, using self-assembly with chips having cavity structures, were investigated for three-dimensional (3D) and hetero integration of complementary metal-oxide semiconductors (CMOS) and microelectromechanical systems (MEMS). By the surface tension of small droplets of 0.5 wt% hydrogen fluoride (HF) aqueous solution, the cavity chips, with a side length of 3 mm, were precisely aligned to hydrophilic bonding regions on the surface of plateaus formed on Si substrates. The plateaus have micro-channels to readily evaporate and fully remove the liquid from the cavities. The average alignment accuracy of the chips with a 1 mm square cavity was found to be 0.4 mm. The alignment accuracy depends, not only on the area of the bonding regions on the substrates and the length of chip periphery without the widths of channels in the plateaus, but also the area wetted by the liquid on the bonding regions. The precisely aligned chips were then directly bonded to the substrates at room temperature without thermal compression, resulting in a high shear bonding strength of more than 10 MPa.

MOSFET Nonvolatile Memory with High-Density Cobalt-Nanodots Floating Gate and $\hbox{HfO}_{\bf 2}$ High-k Blocking Dielectric

Abstract: We report high-performance MOSFET nonvolatile memory with high-density cobalt-nanodots (Co-NDs) floating gate (the density is as high as 4-5 × 1012 /cm 2 and the size is ~2 nm) and HfO2 high-k blocking dielectric. The device is fabricated using a gate-last process. A large memory window, high-speed program/erase (P/E), long retention time, and excellent endurance till 106 P/E cycles are obtained. In addition, the discrete Co-NDs make dual-bit operation successful. The high performance suggests that high work-function Co-NDs combined with high-k blocking dielectric have a potential as a next-generation nonvolatile-memory candidate.

Self-assembly technologies with high-precision chip alignment and fine-pitch microbump bonding for advanced die-to-wafer 3D integration

Abstract: We have demonstrated surface-tension-driven chip self-assembly for 3D stacking of a large number of known good dies (KGDs) on silicon substrates in batch processing. In this work, we employed small droplets of ultra-pure water as a liquid to precisely align chips having fine-pitch indium/gold microbumps with a size/pitch of 5/10 or 10/20μm. By using the self-assembly technique, these chips were aligned in a face-down configuration and flip-chip bonded onto hydrophilic bonding areas formed on silicon substrates. The hydrophilic areas are surrounded by hydrophobic areas that have above 100° in water contact angle. The wettability contrast between the hydrophilic and hydrophobic areas was found to be a key parameter to obtain high alignment accuracy. All chips having the indium/gold microbump arrays were self-assembled with high alignment accuracy of approximately 1μm or superior accuracy, and then, successfully bonded at 200 °C with thermal compression. The resulting resistance measured with the indium/gold daisy chain patterns was sufficiently low (< 20 mΩ/bump) and comparable to one obtained by a conventional mechanical alignment technique.

Development of Si neural probe with optical waveguide for highly accurate optical stimulation of neuron

Abstract: Lots of researchers take great interests in brain science. In this area, measurement devices of the brain have been developed by number of groups, and played an important role. Recently, for neuroengineering applications such as optogenetics, optical stimulation devices which consisted of optical fibers have been reported, and used to deliver light to neurons expressing light sensitive channel proteins. However, accurate stimulation of neurons could not be achieved by using these devices because of optical fibers with a diameter of over 100 μm. Here, we have proposed a novel Si neural probe with micromachined optical waveguide for multiple and precise optical stimulations of neurons. SiN film was employed as the optical waveguide core due to its optical transmission characteristics. Both the light propagation in the optical waveguide and controllability of output patterns of the light were clearly confirmed by optical experiments using a blue laser. In vitro experiments of optical stimulation of neurons using the fabricated Si neural probe were performed. A CA1 area of a thin hippocampal slice obtained from the brain of a transgenic rat expressing Channelrhodopsin-2 (ChR2) was employed. We stimulated neurons optically using the Si neural probe and successfully observed increases of firing rates in neurons accordingly with the light exposure.

Electrical evaluation of Cu contamination behavior at the backside surface of a thinned wafer by transient capacitance measurement

Abstract: The behavior of Cu contamination at the backside surface of a thinned wafer in a three-dimensional (3D) LSI was electrically evaluated by capacitance–time (C–t) analysis In order to electrically evaluate Cu diffusion characteristics, MOS capacitors were fabricated using the thinned wafer of 50 µm and 100 µm thickness, respectively For an accelerated Cu diffusion test, a thin Cu layer was deposited at the back surface as a contamination source Cu atoms were artificially diffused into the substrate by annealing at 200 °C and 300 °C for various times in nitrogen ambient The C–t curves of a MOS capacitor formed on a 100 µm thickness substrate were degraded even after annealing at 200 °C It means that Cu atoms diffuse into the active region and reach the Si–SiO2 interface during relatively low-temperature annealing By increasing time and temperature, the transient time tf is more seriously decreased The C–t curves of the MOS capacitor formed on the Si substrate of 50 µm thickness were more seriously degraded even after the initial annealing at 200 °C for 5 min These results indicate that the Cu contamination issue becomes more severe in a thinner Si substrateThis study shows that C–t analysis is a highly promising method to electrically evaluate the influence of Cu contamination on device reliability in the 3D LSI

Brain probe and method for manufacturing same

Abstract: A brain probe includes: a core probe made from a metal; and n electrode plates attached so as to cover an entire side surface circumference of the core probe and forming n side planes providing an n-angular cross section (n is an integer equal to or greater than 3). Each of the electrode plates is manufactured by a LSI manufacturing process, and provided with at least one electrode and a lead-out wiring extending in a longitudinal direction of a side plane from each of the at least one electrode.

3D integration technology and reliability challenges

Abstract: Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of the super-chip are described. In addition, the reliability challenges such as the mechanical stress/strain and Cu contamination are discussed. Cu TSVs with the diameter of 20-μm induced the maximum compressive stress of ∼1 GPa at the Si substrate adjacent to them after annealed at 300°C. Mechanical strain/stress and crystal defects were produced in extremely thin wafer of 10μm thickness not only during the thinning but also after the bonding using fine-pitch, high-density metal bump. The influences of Cu contamination from the back surface of the thinned wafer and Cu TSVs on device reliability were evaluated by C-t analysis. The C-t curves of MOS capacitors formed in the thinned wafer without IG layer were seriously degraded after annealed at 200°C. The DP stress-relief EG layer at the backside of the thinned wafer exhibited good Cu retardation performance. The C-t curves of the MOS trench capacitor with 10-nm thick Ta barrier layer in Cu TSV were severely degraded after the initial annealing at 300°C for 5min. The degraded C-t curve indicates that the generation lifetime of minority carrier is significantly reduced by Cu contamination.

Multilevel Charge Storage in a Multiple Alloy Nanodot Memory

Abstract: A multilevel charge storage in a multiple FePt alloy nanodot memory is investigated for the first time. It is demonstrated that the memory structure with multiple FePt nanodot layers effectively realizes a multilevel state by the adjustment of gate voltage. Metal oxide semiconductor (MOS) capacitors with four FePt nanodot layers as a floating gate are fabricated to evaluate the multilevel cell characteristic and reliability. Here, the effect of memory window for a nanodot diameter is also investigated, and it is found that a smaller dot size gives a larger window. From the results showing good endurance and retention characteristics for the multilevel states, it is expected that a multiple FePt nanodot memory using Fowler–Nordheim (FN) tunneling can be a candidate structure for the future multilevel NAND flash memory.

Impacts of Microbump-Induced Local Bending Stress in 3D-LSI

Abstract: 1 Dept. of Bioengineering and Robotics, Graduate School of Engineering, Tohoku Univ. 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan Phone: +81-22-795-6909 E-mail: link@lbc.mech.tohoku.ac.jp 2 New Industry Creation Hatchery Center (NICHe), Tohoku Univ. 3 Association of Super-Advanced Electronics Technologies (ASET) 4 Dept. of Biomedical Engineering, Graduate School of Biomedical Engineering, Tohoku Univ.

3D LSI technology and reliability issues

Abstract: 3D integration is the most promising technology to enhance LSI performance beyond scaling theory. 3D LSIs have lots of advantages such as short wiring length, small chip size, and small pin capacitances, which leads to low power dissipation and high processing speed. However, there are still reliability problems to be solved. This paper describes mechanical stresses caused by Cu TSVs and CuSn microbumps and design guideline to minimize stress effects on 3D LSIs.

3D Integration and Reliability

Abstract: Recently three-dimensional (3D) integration technology using through-Si vias (TSVs) has attracted much attention since it gives rise to the higher packing density, shorter interconnections, lower power consumption and hetero-geneous device integration [1][25]. However, there are many concerns in 3D LSIs with TSVs to be solved before the volume production starts. The most serious concern is the heat accumulation in 3D stacked chips. TSVs and metal micro-bumps act as effective heat conductors among many stacked chip layers. Therefore, heat generated at a hot layer is quickly transferred to cool layers and consequently the average temperature of 3D stacked chip increases. Influences of mechanical stress and strain introduced in thinned Si substrates are another concerns in 3D LSIs with TSVs. TSVs and metal microbumps introduce significant mechanical stress and strain into thinned Si substrates. In addition, the LSI chip with thinned Si substrate is more easily affected by metal impurity contamination and crystal defects. Usually intrinsic gettering layer and extrinsic gettering layer are formed in Si substrates of LSI chips to minimize the influences of metal impurity contamination and crystal defects. These gettering layers might be removed by thinning the Si substrate in 3D LSI fabrication process. In this presentation, the influences of mechanical stress and metal impurity contamination in 3D LSIs are discussed.

Energy Band Engineering of Metal Nanodots for High Performance Nonvolatile Memory Application

Abstract: In this work, high density and small size metal nanodots (MND) with different work-functions were fabricated as a floating gate of nonvolatile memory (NVM) devices by self-assembled nanodot deposition (SAND). The energy band engineering of NVM was demonstrated through controlling MND work-function. For single MND layer floating gate NVM, the retention time was improved by choosing high work-function MND. Furthermore, we proposed a new type NVM with a double stacked MND floating gate. Here, the high work-function MND are placed on the top layer and the low work-function MND are placed on the bottom layer. A large memory window and long retention time were obtained. However, the thermal electron excitation is dominant for the electron discharge process during retention. How to reduce the defects in MND layer is important for further improving of memory characteristics.