Showing papers by "Tetsu Tanaka published in 2012"

Multichip-to-Wafer Three-Dimensional Integration Technology Using Chip Self-Assembly With Excimer Lamp Irradiation

Abstract: Self-assembly of multichips with metal microbump electrodes is demonstrated by using water surface tension to increase the stacking throughput/yield and chip alignment accuracy of conventional chip-to-wafer 3-D integration. Three-dimensional microbump interconnects are formed by self-assembly with thermal compression at 200°C. Chips with In-Au microbumps with pitches of 10 and 20 μm are tightly bonded to Si wafers after the flip-chip self-assembly process, resulting in high alignment accuracies of 0.8 and 0.2 μm in the x - and y-directions, respectively. Selective hydrophilization by 172-nm excimer lamp irradiation gives a high wettability contrast between hydrophilic chip bonding areas and hydrophobic surrounding areas on the wafers. This assists high-precision multichip self-assembly. A 2500-In-Au-microbump daisy chain is formed with a yield of 100% by flip-chip self-assembly, and it exhibits ohmic contact. The resistance is sufficiently low for 3-D large-scale integration application, being comparable to that obtained by conventional mechanical chip alignment.

Minimizing the local deformation induced around Cu-TSVs and CuSn/InAu-microbumps in high-density 3D-LSIs

Abstract: One of the most serious reliability issues, the local deformation produced in the stacked LSI die/wafer with respect to the die thickness and the sub-surface structures formed after several stress-relief methods are systematically and extensively studied. From the electron backscatter diffraction (EBSD) analysis, a more than one degree (>1°) of local misorientation is created in the stacked LSI Si around μ-bump region. This induces a large tensile stress above the μ-bump region and relatively small compressive stress in the bump-space region, which leads to an enhancement in the n-MOSFET mobility in the μ-bump region and decrease in mobility at bump-space region. As compared to CuSn system, the InAu μ-bump induced huge amount of tensile stress (> 300 MPa) in the stacked LSI die even for the bonding temperature of 200 °C. The groove structures or scratches found at the background surface after stress relief by plasma etching (PE) or Dry Polishing (DP) severely deteriorates the device characteristics after stacking, owing to the enhanced local deformation as against the stress relief method of chemical mechanical polishing (CMP). Even after 500 cycles of temperature cycle (TC) test, a 20 μm-width Cu-TSV array with 40- μm pitch values induces not only around −570 MPa of compressive stress in the stacked LSI die, but also a large variation in the induced stress values between different TSVs in the same array. For the LSI die/wafer thickness of anything less than 50 μm, the Young modulus (E) and Hardness (H) of the thinned die no longer behaves like a bulk single crystal Si, which severely increases the reliability risks in the highly integrated 3D-LSIs.

A very low area ADC for 3-D stacked CMOS image processing system

Abstract: This paper presents a very small circuit area analog-to-digital converter (ADC) for three-dimensional (3-D) stacked CMOS image processing system. To realize high-speed image sensor, we have proposed a block-parallel signal processing with 3-D stacked structure. The proposed block-parallel analog signal processing elements contains CMOS image sensor, correlated double sampling (CDS) array, and ADC array. Each circuit layer is vertically stacked and electrically connected by through-Si vias (TSVs), which can improve sensor performance. On the other hand, the block-parallel system requires ADC with extremely low-power and small circuit area. Therefore, the trade-off among area, power dissipation and conversion speed is important factor, and critical challenge. To achieve extremely low circuit area and low power dissipation, ADC designed in the prototype chip for fundamental evaluation employed the time interleaved charge-redistribution successive approximation (SAR) method. An implemented 9-bit prototype in a 90 nm CMOS technology occupies 100×100 μm2, achieves an ENOB of 7.28 bit at a conversion rate of 4 MS/s. The power dissipation is 381μW with supply voltage of 1.0V and 4 MS/s conversion rate.

Through-Silicon Photonic Via and Unidirectional Coupler for High-Speed Data Transmission in Optoelectronic Three-Dimensional LSI

Abstract: We develop Si-core through-silicon photonic via (TSPV) and unidirectional coupler for low-loss and high-speed data transmission in an optoelectronic 3-D LSI. The TSPVs, comprising a Si-core and SiO2 cladding, were fabricated simultaneously with Cu TSVs. The characteristics of light confinement of the TSPV were measured using a near-field pattern measurement. The spot light area was well confined within the TSPV without interference from the lights. The optical intensity that passed through the TSPV was 20% higher than that which passed through the Si substrate. The unidirectional optical coupler with two mirrors showed higher coupling efficiency. Laser light can be efficiently propagated to a planar Si waveguide through the TSPV and the unidirectional coupler.

New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding

Abstract: We proposed a new chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding. In the hybrid self-assembly-based chip-to-wafer 3D integration (HSA-CtW), liquid surface-tension-driven chip self-assembly is combined with high-speed robotic pick-and-place chip assembly and electrostatic multichip temporary bonding. Hybrid self-assembly can realize high-throughput chip assembly of above 10,000 chips/hour with a high alignment accuracy of < 1 μm. The electrostatic multichip temporary bonding technique enabled stress-free direct bonding of self-assembled chips. We obtained good electrical characteristics from 3D stacked chips fabricated by HSA-CtW using Cu/SnAg microbumps and Cu-TSVs.

A 37 × 37 pixels artificial retina chip with edge enhancement function for 3-D stacked fully implantable retinal prosthesis

Abstract: To restore visual sensation of blind patients suffering from age-related macular degeneration (AMD) and retinitis pigmentosa (RP), we have been developing a fully implantable retinal prosthesis with three-dimensional (3-D) stacked artificial retina chip. This chip has layered structure similar to human retina and includes such functions as converting incident light into electrical signal, processing visual information, and generating stimulus current pulse. In this paper, we have developed a photoreceptor chip with selectable sensitivity circuit and a stimulus current generator chip with edge enhancement function using four-neighbor Laplacian filter for 3-D staked artificial retina chip. As results, the 37 × 37 pixels photoreceptor chip correctly converted incident light into electrical signal, and the edge enhancement and stimulus current generator chip with edge enhancement function successfully emphasized the edges of input images and generated biphasic stimulus current patterns. By stacking these two chips, artificial retina chip having a pixel number of 37 × 37, a pixel size of 75 × 75 μm2, and the fill-factor more than 27%, will be realized.

Inhibition of IκB phosphorylation prevents load-induced cardiac dysfunction in mice.

Abstract: Pressure overload is known to be a cause of cardiac hypertrophy that often transits to heart failure. Although nuclear factor (NF)-κB is a key factor in the progression of cardiac hypertrophy, its ...

Impact of Cu diffusion from Cu through-silicon via (TSV) on device reliability in 3-D LSIs evaluated by transient capacitance measurement

Abstract: The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI was electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10-nm and 100-nm thicknesses (at the wafer surface) were fabricated. The C-t curves of the trench capacitors with 10-nm thick Ta layer were severely degraded even after the initial annealing for 5min. It means that Cu atoms diffuse into the active area from the Cu TSV through scallop portions with extremely thin Ta layer in TSVs, and consequently, the generation lifetime of minority carrier is significantly reduced. Meanwhile, the C-t curves of the trench capacitors with 100-nm thick Ta layer exhibit no change after annealing up to 60min at 300°C, but show significant degradation after the initial annealing for 5min at 400°C. The C-t analysis is a useful method to electrically characterize the influence of Cu contamination from the Cu TSV on device reliability in fabricated LSI wafers.

Ultrafast parallel reconfiguration of 3D-stacked reconfigurable spin logic chip with on-chip SPRAM (SPin-transfer torque RAM)

Abstract: We have developed novel 3D-stacked reconfigurable spin logic chip having ultrafast on-chip SPRAM to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using 3D integration technology. From the SPRAM cell evaluation, the fastest write speed of 5 ns was obtained in the circuits. To realize higher performance reconfigurable LSIs, parallel reconfiguration was fully demonstrated for the stacked reconfigurable spin logic chips for the first time. Both ultrafast on-chip SPRAM and 3D-stacked structure will open a new era of reconfigurable LSIs.

High-step-coverage Cu-lateral interconnections over 100 µm thick chips on a polymer substrate—an alternative method to wire bonding

Abstract: We propose a novel chip in the polymer board interconnect method for packaging different kinds of chips on a wafer level, where conventional wire bonding may not be possible due to either space or mechanical constraints. High-step-coverage copper (Cu)-lateral interconnects formed over 100??m thick Si chips by the electroplating method have been investigated for their microstructure and electrical characteristics, using the field emission scanning electron microscope and semiconductor parameter analyzer (Agilent, 4156C). The obtained coverage ratios (i.e. the layer thickness on the chip surface to the sidewall of the chip) for each formed layer, i.e. the tantalum barrier layer, Cu seed layer, SiO2?dielectric layer and electroplated Cu layer, were 3:1, 3:1, 1.5:1 and 1:1, respectively. The measured mean electrical resistances for 36??m???2000??m and 58??m???2000??m interconnect lines were respectively 31.1 and 24?m?, and the difference between measured and calculated resistance values was less than 5%. The good quality of as-fabricated Cu-lateral interconnects was evidenced from the observed low resistance values for isolated interconnects and the linear change in daisy chain resistance with the number of interconnects. More importantly, even at a high operating temperature of 150??C, the resistance value of the Cu-lateral interconnect over the integrated chip was very close to that of the resistance value of interconnect on the plain wafer. The suitability of this technique in integrating various chips heterogeneously was validated from the no observed change in transistor behavior due to this technique. Since this is a CMOS compatible interconnection method between the polymer substrate and chip, it can readily be scaled up to the wafer level.

Low-Resistance Cu-Sn Electroplated–Evaporated Microbumps for 3D Chip Stacking

Abstract: Low-resistance copper-tin (Cu-Sn) microbumps, with sizes varying from 5 μm × 5 μm to 20 μm × 20 μm and formed by electroplating–evaporation bumping (EEB) technology for three-dimensional integration of large-scale integrated chips, have been evaluated for their microstructure and electrical resistance. It was inferred from x-ray diffraction data that the formation of low-resistance Cu3Sn intermetallic compound (IMC) is facilitated at higher bonding temperature. Electron probe microanalysis mapping showed that, even before bonding, Cu-Sn IMCs were formed at the interface between Cu and Sn, whereas they were sandwiched between the Cu of the upper and lower microbumps after bonding. Electron backscatter diffraction analysis revealed that the crystal orientation of Sn grains was sharply localized in the (100) orientation for physical vapor deposited (PVD) sample, while electroplated Sn film exhibited a mixed crystal orientation in all (100), (110), and (001) axes. A resistance value of ~35 mΩ per bump was obtained for Cu-Sn microbumps with area of 400 μm2, which is several times lower than the resistance value reported for Cu-Sn microbumps fabricated by a pure electroplating method. The low resistance value obtained for EEB-formed Cu-Sn microbumps after bonding is explained by (i) the reduced surface roughness for evaporated Sn, (ii) the high degree of crystal grain orientation resulting from layer-by-layer growth in the PVD Sn, despite their smaller grain size, and (iii) the absence of impurity segregation at grain boundaries.

Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system

Abstract: We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.

Thermomechanical reliability challenges induced by high density Cu TSVs and metal micro-joining for 3-D ICs

Abstract: The thermo-mechanical reliability challenges induced by high-density Cu TSVs and metal micro-joining are discussed. Cu TSV with the diameter of 20-µm induced the maximum compressive stress of ∼1 GPa at the Si substrate adjacent to them after annealed at 300°C. Depart from Cu TSV, the stress/strain in Si substrate changed to tensile stress and finally going to zero, where the TSV pitch is larger than twice of TSV size. However, in high density Cu TSV array with small TSV pitch, the Si substrate within small TSV spacing keep large compressive stress, which will seriously affect the mobility in active Si area, and thus device characteristics. Also, these large compressive stress leads to not only extrusion and peeling of Cu TSV, but also die cracking. The thermo-mechanical stress was produced during the bonding using high-density metal bumps. CuSn bump of 20-µm size has induced compressive stress of 140MPa beneath Si wafer surface, and it penetrates deeper area with large stress value after the bonding. The drain current and electron mobility of n-MOSFET which was located 15µm distance from microbump are changed by ∼10 % due to the local tensile stress of 500 MPa induced by microbump. Electron mobility changed varying with the distance from microbump. Influences of mechanical stress induced by Cu TSVs and microbump-underill joining on device characteristics were also evaluated.

Impact of Cu Contamination on Memory Retention Characteristics in Thinned DRAM Chip for 3-D Integration

Abstract: The influence of Cu diffusion at the backside surface of a thinned dynamic random access memory (DRAM) chip for 3-D integration on memory retention characteristics was electrically evaluated. A DRAM test chip was bonded to a Si interposer at 300 °C for 2 min and thinned down to 30-μm thickness. The DRAM cell characteristics, which show 50% failure at 200 μs, were not degraded from the packaged sample (prethinning) even after chip bonding, chip thinning, and no-Cu postannealing for 30 min at 300 °C. Meanwhile, the DRAM cell array shows 50% failure at 70 μs after an intentional Cu diffusion from the backside surface for 30 min at 300 ° C. It means that Cu atoms at the back surface reach the Si-SiO2 interface of the front surface in active areas and cause functional failures such as increasing carrier recombination rate, consequently shortening retention time. However, the NMOS transistor characteristics show no significant change even after Cu diffusion. The on-current performance characterized by majority carriers is not an effective criterion to characterize sensitively the Cu contamination effect.

Non-conductive film and compression molding technology for self-assembly-based 3D integration

Abstract: Two key technologies consisting of chip-to-wafer bonding through a non-conductive film (NCF) and wafer-level packaging using compression molding were studied for self-assembly-based 3D integration, especially reconfigured wafer-to-wafer stacking. 4-mm-by-5-mm chips having 20-μm-pitch Cu-SnAg microbumps were successfully bonded to wafers through NCF. The resulting daisy chain obtained from the chip-to-wafer structure showed low contact resistance of approximately 50 MΩ/bump. Compression molding was implemented to a chip-on-wafer structure. Grinding of the chip-on-wafer structure gave low total thickness variation (TTV) within 1 μm and the following CMP led good planarization capability.

Pillar-shaped stimulus electrode array for high-efficiency stimulation of fully implantable epiretinal prosthesis

Abstract: We developed a pillar-shaped microelectrode array (MEA) with varying heights for enhancing the spherical conformity of fully implantable epiretinal prosthesis comprising a 3D stacked retinal chip The fabricated MEA is composed of 100 pillar electrodes with heights ranging from 60 to 80 µm The Pt-coated Cu pillar electrode with a surface diameter of 70 µm and a height of 75 µm and the Pt planar electrode with a surface diameter of 70 µm have 246 and 125 kΩ impedances, respectively, at 1 kHz in vitro experiment The pillar electrode shows lower impedance than the planar electrode because of a larger surface area However, to avoid cross-talking between pillar electrodes, we developed a sidewall passivation process of the pillar electrode by using the surface tension of polyimide The impedance of the isolated pillar electrode 116 kΩ at 1 kHz is similar to the impedance of the planar electrode, because they have similar electrode surface areas The pillar-shaped MEA shows a better spherical conformity

High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs

Abstract: The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI was electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10-nm and 100-nm thicknesses (at the surface) were fabricated. The C-t curves of the trench capacitors with 10-nm thick Ta layer were severely degraded even after the initial annealing for 5 min at 300°C. It means that Cu atoms diffuse into the active area from the Cu TSV through scallop portions with extremely thin Ta layer in TSVs, and consequently, the generation lifetime of minority carrier is significantly reduced. However, the C-t curves of the trench capacitors with 100-nm thick Ta layer exhibit no change after annealing up to 60min. Based on the C-t evaluation results, we developed high reliable and fine-size of 5-μm diameter backside Cu TSV to achieve high reliability and high-end 3-D LSIs.

Locally induced stress in stacked ultrathin Si wafers: XPS and μ-Raman study

Abstract: Induced local stress arising from local deformation of top silicon die in the vertically stacked LSI die has been investigated via x-ray photoelectron spectroscopy (XPS) and micro-Raman spectroscopy (μRS). The large positive shift in the core level Si-2s and Si-2p XP spectra for the thinned die revealed that thinned dies were under heavy stress/strain even before stacking. The core level binding energy shift, ΔEb for Si-1s core level and the relative chemical shift ΔEr for Si in the vertically integrated die system showed that the stacked Si dies were under different stresses in the μ-bump and the bump-space regions. It was also inferred from the μRS results that the stacked 10 μm-thick-Si dies were under large tensile strain of >1.5 GPa and a relatively small compressive stress of ∼0.5 GPa in the μ-bump and bump-space region, respectively.

High density Cu-TSVs and reliability issues

Abstract: Reliability issues such as thermo-mechanical stress, extrusion of via metal, and die-cracking caused by high density Cu-TSVs in 3D-LSI Si die/wafer after wafer thinning and bonding have been systematically investigated respectively using micro-Raman spectroscopy, laser microscopy, and optical microscopy techniques. It is inferred that (i) for the TSV pitch value of less than twice the TSV-width, the remnant stress present in the Si at the TSV space region is turned to be only compressive, i.e. in the lateral direction, the compressive stress produced by the adjacent TSVs overlapped to each other; for the TSV pitch values of greater than two times the TSV-width, the compressive stress in the Si at the vicinity of TSV is followed by the tensile stress and beyond that it becomes stress free at the TSV space region; (ii) Irrespective of the TSV shape and size, the lateral extrusion of Cu occurs at the TSV space region. The lateral extrusion becomes prominent for the larger TSV size values and the higher bonding temperatures. The lateral extrusion is larger for the 20 μm-width TSV annealed at the higher temperature (∼4 μm @ 400 °C) than for the TSV annealed at lower temperature (a maximum of only 1.5 μm @ 200 °C); (iii) Cracking of LSI die/wafer occurs at the periphery of the TSV array for very fine pitch values, and for larger pitch values cracking occurs in between TSVs.

Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration

Abstract: We developed a novel detachable bonding process by controlling wettability of a bonding surface. A high hydrophobic surface was formed in the bonding area for adhesion blocking. We applied an adhesive material with high thermal resistance at around 350 °C. In this paper, the bonding characteristics of the novel detachable bonding process was estimated by evaluating the shear strength and the dissolution time of adhesive material varying the ratio of hydrophobic area to the hydrophilic area using 5 mm2 size chip. Based on the evaluation results of the shear strength and the de-bonding time, 10 % of the hydrophilic area is suitable condition for our novel chip-level 3D integration process.

Chip-based hetero-integration technology for high-performance 3D stacked image sensor

Abstract: We have developed a 3D-stacked image sensor chip composed of CMOS image sensor (CIS) layer, correlated double sampling circuit (CDS) layer, and analog-to-digital converter (ADC) array layer using the chip-based 3D heterogeneous integration technology Three kinds of chips, CIS chip, CDS chip, and ADC chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor

W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress

Abstract: High density 3D-LSI with W-TSV for signal line and Cu-TSV for power/GND line, and Cu-TSV containing W stress absorbing layers were investigated for the induced thermo-mechanical stress in 3D-LSI Si die/wafer after wafer thinning and bonding using micro-Raman spectroscopic technique. Stress mapping analysis revealed that W-TSV has induced less thermo-mechanical stress in LSI Si, whereas the Cu-TSV has induced large amount of stress. Further, Cu-TSV with W stress absorbing layer showed much reduced residual thermo-mechanical stress as compared to the pure Cu-TSV, i.e for 6 μm diameter Cu-TSV with W layer showed −300 MPa of compressive stress after heating at 400 °C. This property can be readily employed to minimize the residual thermo-mechanical stress in the bonded high density 3D-LSI.

Heterogeneous 3D integration technology and new 3D LSIs

Abstract: A new 3-D integration technology and heterogeneous integration technology called a super-chip integration is described. A number of known good dies (KGDs) with different sizes and different devices are simultaneously aligned and bonded onto lower chips or wafer by a chip self-assembly method using the surface tension of liquid in the super-chip integration. Possibilities for new system-on-a chip and heterogeneous LSIs by 3D super-chip integration such as 3D stacked multicore processor with self-test and self-repair function, GPU stacked 3D image sensor with extremely fast processing speed and 3D stacked reconfigurable processor with spin memory are discussed.

Study for CMOS device characteristics affected by ultra thin wafer thinning

Abstract: Wafer thinning and fabrication of through-Si via (TSV) and micro-bump are key processes in 3D LSI Because of mechanical stress under these processes, electrical deviations of CMOS devices such as DRAM are occurred And the other hand, the thinner Si chip becomes, the more risky impurity ion contamination attacks the Si device We will report about the result of DRAM retention time reduced to one third by Cu contamination whose thickness is less than 50μm And also report about the example for investigation of several gettering methods

Self-assembly-based 3D integration technologies

Abstract: We have proposed and developed massively parallel chip self-assembly technologies using surface tension of liquid for advanced chip-to-wafer 3D integration. Here, we introduce flip-chip self-assembly in batch processing and reconfigured wafer-to-wafer 3D integration as a new chip-to-wafer 3D integration approach using self-assembly.

Temporary bonding strength control for self-assembly-based 3D integration

Abstract: We have demonstrated bonding strength control for self-assembly-based 3D integration in which many chips are instantly assembled on a wafer all at once by using liquid droplets, and then, temporarily bonded to the wafer. The wafer is named Reconfigured Wafer. The self-assembly-based multichip-to-wafer 3D stacking is called reconfigured-wafer-to-wafer 3D integration. The alignment accuracy is found to be within 1 μm and the temporal bonding strength is well controlled by the quality of oxides as a bonding interface material, liquid types (concentration of additives), total bonding area, and surface roughness of the oxides. The self-assembled and temporarily bonded chips are successfully transferred to another wafer in a face-to-face bonding manner in batch processing.

Development of Si Opto-Neural Probe with Multiple Optical Waveguides and Metal-cover as Versatile Tool for Optogenetics

Abstract: 1 Department of Biomedical Engineering, Graduate School of Biomedical Engineering, Tohoku University 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan Phone: +81-22-795-6258, Fax: +81-22-795-6908, E-mail: link@lbc.mech.tohoku.ac.jp 2 Department of Biology and Neuroscience, Graduate School of Life Sciences, Tohoku University 3 Department of Applied Information Science, Tohoku University 4 Department of Physiology, Tohoku University School of Medicine

Optoelectronic Heterogeneous Integration Tech. Using Reductant-assisited Self-Assembly with Cu/Sn Microbump

Abstract: 1 Sumitomo Bakelite Co., Ltd., 20-7 Kiyohara Industrial Park, Utsunomiya 321-3231, Japan 2 Department of Bioengineering and Robotics, Graduate School of Engineering, Tohoku University 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan Phone: +81-22-795-6909, E-mail: ito@lbc.mech.tohoku.ac.jp 3 New Industry Creation Hatchery Center, Tohoku University 4 Deptartment of Biomedical Engineering, Graduate School of Biomedical Engineering, Tohoku University