Showing papers by "Tetsu Tanaka published in 2015"

Development of highly-reliable microbump bonding technology using self-assembly of NCF-covered KGDs and multi-layer 3D stacking challenges

Abstract: We have proposed a new multichip-to-wafer 3D stacking method with high throughput and high yield based on a capillary self-assembly method using liquid droplets. In this paper, we optimized conditions in self-assembly and microbump bonding using non-conductive film (NCF)-covered known good dies (KGDs). Self-assembly of the NCF-covered KGDs provided high chip alignment accuracy within approximately 1 µm. After the self-assembly and a subsequent thermal compression, resultant microbump chains composed of over 7,000 microbump joints exhibited good electrical properties of 32 mΩ/joint without bridge short and open failures. The microbump joint resistance varied within 5% of the initial values after thermal cycle test (TCT) of 1,000 cycles. In addition, we demonstrated a multi-layer 3D stacking by the self-assembly method with the NCF-covered KGDs.

Applications of three-dimensional LSI

Abstract: To overcome various concerns due to scaling-down device size in future large-scale integration (LSI), it is indispensable to introduce a new concept of heterogeneous three-dimensional (3D) integration in which various kinds of device chips with different sizes, devices, and materials are vertically stacked. To achieve such heterogeneous 3D integration, the key technology of self-assembly and electrostatic (SAE) bonding has been developed. The heterogeneous 3D integration technology with the SAE bonding method has enabled 3D heterogeneous stacking of different types of chips such as the compound semiconductor device chip, photonic device chip, and spintronic device chip on complementary metal oxide semiconductor chips. A 3D image sensor with extremely fast processing speed and a 3D microprocessor with a self-test and self-repair function for future automatic driving vehicles are typical examples of heterogeneous 3D LSIs which we fabricated by the SAE bonding method.

Role of Bath Composition in Electroless Cu Seeding on Co Liner for through-Si Vias

Abstract: To enable Cu fill of through-Si vias (TSV) with a high aspect ratio (diameter 3 μm, depth 50 μm), the electroless deposition of a Cu seed on Co liner material was investigated. The reducing agent glyoxylic acid showed anodic oxidation on Co, which did not appear for the case of formaldehyde. From electrochemical analysis, an optimized bath composition caused limited Co corrosion during the electroless Cu nucleation phase. The concentration ratio of the complexing agent (ethylenediaminetetraacetic acid) and copper was found to strongly impact the liner corrosion; in case free complexing agent is present in the bath, the Co corrosion was assisted by complexation and replacement reactions. A continuous seed layer could be deposited in the entire TSV, which enabled the filling by electrochemical deposition (ECD). The substantially thinner total copper overburden generated for this combination of a wet-chemical seed deposition and an ECD fill process contributes to a cost reduction of its chemical mechanical polishing (CMP). © The Author(s) 2014. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0131501jss] All rights reserved.

Vertical-cavity surface-emitting laser chip bonding by surface-tension-driven self-assembly for optoelectronic heterogeneous integration

Abstract: Twelve-channel vertical-cavity surface-emitting laser (12-ch VCSEL) chips are heterogeneously self-assembled on Si and glass wafers using water surface tension as a driving force. The VCSEL chips have a high length-to-width aspect ratio, that is, 3 mm long and 0.35 mm wide. The VCSEL chips are precisely self-assembled with alignment accuracies within 2 ?m even when they are manually placed on liquid droplets provided on the host substrate. After the self-assembly of the VCSEL chips and the subsequent thermal compression, the chips successfully emit 850 nm light and exhibit no degradation of their current?voltage (I?V) characteristics.

Novel reconfigured wafer-to-wafer (W2W) hybrid bonding technology using ultra-high density nano-Cu filaments for exascale 2.5D/3D integration

Abstract: In order to solve the critical issues of current standard chip-to-wafer (C2W)/wafer-to-wafer (W2W) hybrid bonding technologies, we propose novel reconfigured wafer-to-wafer (W2W) hybrid bonding technology using three types of scaled tiny electrodes with slightly extruded structure and unique adhesive layers for ultra-high density 2.5D/3D integration applications. Especially, we developed a high stacking yield hybrid bonding technology using unique anisotropic conductive film composed of ultra-high density nano-Cu filaments for exascale 2.5D/3D integration. Multi numbers of TEG die with 7mm × 23mm size are simultaneously aligned with high accuracy around 1um by chip self-assembly method and thermal-compression bonding in wafer-level. Totally 3,898,000 of 4,309,200 electrodes with 3um diameter/6um pitch in each TEG chip are well intact-bonded by new hybrid bonding technology using ultra-high density nano-Cu filaments which gives rise to the joining yield of 90%.

Plasma assisted multichip-to-wafer direct bonding technology for self-assembly based 3D integration

Abstract: We demonstrated plasma-assisted multichip-to-wafer direct bonding for self-assembly based 3D integration processes. We mainly evaluated the bonding yields and bonding strengths of dies obtained by multichip-to-wafer direct oxide-oxide bonding, and compared with wafer-to-wafer direct oxide-oxide bonding in their bonding properties. In this study, we employed thermal oxide and chemical mechanical polish (CMP)-treated oxide formed by plasma-enhanced chemical vapor deposition (PECVD) with tetraethyl orthosilicate (TEOS) as bonding interfaces, and in addition, N 2 or Ar plasmas were used for the surface activation. We finally introduce multichip-to-wafer direct oxide-oxide bonding between self-assembled dies and wafers having the PECVD-oxide layer.

Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers

Abstract: High yield reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology is proposed for ultra-high density 2.5D/3D integration applications. New mCoW hybrid bonding technology use shallow-recess oxide structure, electro-less plated capping layers, and thin glue adhesive layer below 1um to avoid the issues of current standard CoW bonding technology. Multi numbers of TEG die with 7mm × 23mm size are simultaneously aligned with high accuracy around 1um using chip self-assembly technology and thermal-compression bonded by in batch. In the TEG chip, totally 684,000 electrode daisy chain comprising of 3um diameter/6um pitch tiny Cu electrodes are well intact joined by new reconfigured mCoW hybrid bonding technology.

Area-Efficient and Wide-Range Impedance Analysis Circuit for Multichannel High Quality Brain Signal Recording System

Abstract: To enable chronic and stable neural recording, we introduce an implantable multichannel neural recording system with impedance analysis function. An important thing for high quality neural signal recording is how well recording electrodes are interfaced to tissue. We have proposed an impedance analysis circuit with very small circuit area which is implemented in multichannel neural recording and stimulating system. In this paper, we focus on the design of analysis circuit configuration and voltage measurement circuit. The proposed circuit has a very small circuit area of 0.23 mm 2 designed with 0.18-μm CMOS technology, and measures interface impedance with ultra wide range from 10 kΩ to 10 MΩ. In addition, we were also successful in acquiring impedances using agarose gel experiments.

Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC

Abstract: Three-dimensional IC (3D IC) has attracted much attention as a promising method to enhance IC performance. Recently, great interests in mechanical reliability are increasing among 3D IC researchers for production of 3D IC. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive called underfill material. In general, coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE difference induces local bending stress in thinned IC chips. This local bending stress would affect transistor reliability in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. In this work, we present design guideline of microbump layout which can suppress the local bending stress in 3D-stacked several thin IC chips.

Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM

Abstract: Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip were evaluated. The retention characteristics of memory cells were degraded depending on the decreased chip thickness, especially dramatically degraded below 40-μm thickness in the case with under-fill, meanwhile, the retention characteristics were relatively not so degraded until to 30-μm thickness, but suddenly degraded below 20-μm thickness in the case without under-fill. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300oC annealing. Meanwhile, the retention characteristics in the thinned DRAM chip which was DP-treated did not degrade regardless of the well structure. The retention characteristics of some memory cell arrays with Cu TSV arrays began to degrade after annealing at 300oC for 30min. As the annealing temperature increase higher than 400oC, Cu atoms more spread out into larger area in the DRAM chip via poor barrier layers.

Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study

Abstract: 3D-LSI chip containing through-silicon-via (TSV, diameters ranging from 5 µm to 30 µm) with two different dielectric liners has been investigated for thermo-mechanical stress (TMS) in Si via micro-Raman spectroscopy and micro-X-ray diffraction analysis. Both the micro-Raman and micro-X-ray diffraction results revealed that the low-k CVD-grown dielectric polyimide (PI) liner tremendously reduces the TMS in the vicinal Si as well as the Si sandwiched between TSVs. It can be explained that the observed smaller TMS values for TSVs with PI is owing to the partial accommodation of the expanded Cu during thermal cycling by the low modulus, soft PI.

JSS FOCUS ISSUE ON ADVANCED INTERCONNECTS :M ATERIALS ,P ROCESSING, AND RELIABILITY Role of Bath Composition in Electroless Cu Seeding on Co Liner for through-Si Vias

Abstract: To enable Cu fill of through-Si vias (TSV) with a high aspect ratio (diameter 3 μm, depth 50 μm), the electroless deposition of a Cu seed on Co liner material was investigated. The reducing agent glyoxylic acid showed anodic oxidation on Co, which did not appear for the case of formaldehyde. From electrochemical analysis, an optimized bath composition caused limited Co corrosion during the electroless Cu nucleation phase. The concentration ratio of the complexing agent (ethylenediaminetetraacetic acid) and copper was found to strongly impact the liner corrosion; in case free complexing agent is present in the bath, the Co corrosion was assisted by complexation and replacement reactions. A continuous seed layer could be deposited in the entire TSV, which enabled the filling by electrochemical deposition (ECD). The substantially thinner total copper overburden generated for this combination of a wet-chemical seed deposition and an ECD fill process contributes to a cost reduction of its chemical mechanical polishing (CMP). © The Author(s) 2014. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any

Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors

Abstract: Three-dimensional integrated circuit (3D IC) is one of the promising ways to enhance IC performance. Each IC chip is mechanically connected by organic adhesive and metal microbumps. Coefficient of thermal expansion (CTE) mismatch between materials causes local bending stress in IC chips, leading to negative effects in IC performance. In this study, we have fabricated a test structure with DRAM cell array having planar MOS capacitors. Using the test structure, we measured both DRAM chip bending profiles and retention time modulations of DRAM cell array. Consequently, we have successfully demonstrated that the local bending stress in IC chips can be two-dimensionally evaluated using the DRAM cell array with planar MOS capacitances. This evaluation methods leads to realization of 3D IC with high reliability.

Impact of deep-via plasma etching process on transistor performance in 3D-IC with via-last backside TSV

Abstract: 3D-IC (3D-stacked integrated circuit) requires lots of through-Si vias (TSVs) and metal microbumps for electrical connection among stacked LSI chips to realize higher performance beyond 2D-IC. However, plasma etching process for via-last backside TSV formation could damage many transistors used in the 3D-IC. In this study, plasma-induced charge-up damages on transistor characteristics during viahole etching have been investigated using test structures flipchip bonded on Si interposer. Additionally, antenna rules for the 3D-IC layout and process design were also mentioned.

A high reliability module with thermoelectric device by molding technology for M2M wireless sensor network

Abstract: This paper presents the fabrication of a new energy harvesting module that uses a thermoelectric device (TED) by using molding technology. Through molding technology, the TED and circuit board can be properly protected and a heat-radiating fin structure can be simultaneously constructed. The output voltage per heater temperature of the TED module at 20 °C ambient temperature is 8 mV K−1, similar to the result with the aluminum heat sink which is almost the same fin size as the TED module. The accelerated environmental tests are performed on a damp heat test, which is an aging test under high temperature and high humidity, highly accelerated temperature, and humidity stress test (HAST) for the purpose of evaluating the electrical reliability in harsh environments, cold test and thermal cycle test to evaluate degrading characteristics by cycling through two temperatures. All test results indicate that the TED and circuit board can be properly protected from harsh temperature and humidity by using molding technology because the output voltage of after-tested modules is reduced by less than 5%. This study presents a novel fabrication method for a high reliability TED-installed module appropriate for Machine to Machine wireless sensor networks.

Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding

Abstract: Two types of high-throughput and high-precision multichip-to-wafer 3D stacking approaches are demonstrated: one is non-transfer stacking and the other one is transfer stacking. Both the stacking approaches employ a self-assembly technologies using liquid surface tension. In the former stacking scheme, large number of chips having 20-µm-square Cu/SnAg microbumps are directly self-assembled face-down on an interposer wafer, like flip-chip bonding. On the other hand, in the latter stacking scheme, the many chips having the microbumps are self-assembled face-up on a carrier wafer with bipolar electrodes for electrostatic chucking. Then, the latter chips are transferred from the carrier to another interposer in wafer-level processing. The alignment accuracies are evaluated and compared between the two stacking approaches. The resulting daisy chains show good electrical properties comparable to conventional flip-chip bonding.

Advanced 2.5D/3D hetero-integration technologies at GINTI, Tohoku University

Abstract: The Global Integration Initiative (GINTI) is 8/12-inch R&D foundry fab for the research and development of new 2.5D/3D integration technologies and creative applications. GINTI offers a broad range of services to meet the mounting R&D needs of the semiconductor industry and related industries. GINTI provides a cost-competitive process development infrastructure in a manufacturing-like fab environment and a low-cost, short TAT prototyping of proof of concepts using commercial/customized 2D chip/wafer, and a base-line process set-up for the pilot production of creative 3D systems. GINTI aims to provide Tohoku University's advanced 2.5D/3D integration technologies into electronic industries to accelerate the commercialization of innovative 3D technologies and applications into real, manufacturing-ready technology solutions with FAST. This paper introduces advanced 2.5D/3D hetero-integration technologies developed by GINTI/Tohoku University.

Plasma Assisted Multichip-to-Wafer Direct Bonding Technology

Abstract: We demonstrated plasma-assisted multichip-to-wafer direct bonding for self-assembly based 3D integration processes. We mainly evaluated the bonding yields and bonding strengths of dies obtained by multichip-to-wafer direct oxide-oxide bonding, and compared with wafer-to-wafer direct oxideoxide bonding in their bonding properties. In this study, we employed thermal oxide and chemical mechanical polish (CMP)-treated oxide formed by plasma-enhanced chemical vapor deposition (PECVD) with tetraethyl orthosilicate (TEOS) as bonding interfaces, and in addition, N2 or Ar plasmas were used for the surface activation. We finally introduce multichip-to-wafer direct oxide-oxide bonding between self-assembled dies and wafers having the PECVDoxide layer.