Showing papers by "Tetsu Tanaka published in 2017"

Remarkable Suppression of Local Stress in 3D IC by Manganese Nitride-Based Filler with Large Negative CTE

Abstract: A local bending stress is induced by coefficient of thermal expansion (CTE) mismatch between underfill material and metal microbumps in three-dimensional IC (3D IC). A high concentration of filler in underfill is effective to suppress the local bending stress. However, it is difficult to apply high concentration of filler due to fine pitch microbumps. On the other hand, manganese nitride-based compound has large negative CTE compared with conventional negative-CTE materials. In this study, we have investigated the effect of manganese nitride-based filler on local bending stress induced by CTE mismatch between underfill and metal microbumps in 3D IC. We observed that manganese nitride-based filler can decrease CTE of underfill compared with conventional silica-based filler. This result indicated that manganese nitride-based filler can reduce keep-out-zone (KOZ) in 3D IC by local bending stress suppression.

Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration

Abstract: A self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3-D integration. In this paper, water surface tension-driven chip assembly is combined with electrostatic adhesion to keep high alignment accuracies obtained by the capillary self-assembly process. The self-assembled chips can be firmly fixed on an SAE carrier wafer by electrostatic adhesion, and then, the chips can be readily detached from the carrier by discharging and transferred to another carrier with a temporary adhesive. This paper describes the impact of chip clamping forces and electrical reliability of the SAE carrier on chips to be 3-D stacked in chip-to-wafer configuration. Through-Si via formation is demonstrated by using a via-last 3-D integration process based on the SAE carrier. The demonstration shows that the SAE carrier maintains higher chip alignment accuracies than does conventional carrier without electrostatic adhesion.

Minimized hysteresis and low parasitic capacitance TSV with PBO (polybenzoxazole) liner to achieve ultra-high-speed data transmission

Abstract: Through-Si-via (TSV) with polymer liner formation has attracted considerable attention because a polymer liner can be formed easily by spin coating, and it has low dielectric constant and good coverage along the TSV surface. A polyimide (PI) was used as the polymer liner of TSV. However, there is a high charge-trap density in the PI layer. These charge traps leads to modulation of the parasitic capacitance present between the TSV metal and the Si substrate. Therefore, in this paper, we propose the deployment of polybenzoxazole (PBO) as the polymer-liner material of TSV for minimizing the capacitance modulation. In this study, a metal-insulator-semiconductor capacitor with blind TSV structure was fabricated with PBO and PI liners. Further, capacitance-voltage (C-V) characteristics of the fabricated MOS capacitor were evaluated. In case of the PBO liner, remarkable suppression of the C-V curve shift was observed as compared to that of the PI liner. These results indicate that the PBO is a promising TSV liner material for realizing high-performance, high-reliability, and low-cost three-dimensional stacked ICs.

3D-IC technology and reliability challenges

Abstract: Three-dimensional (3D) ICs using TSVs are the most promising candidate for high performance and low power computing since they have lots of advantages such as short wiring length, small chip size, and small pin capacitances, as shown in Fig. 1 [1]. Until now, several kinds of 3D-ICs including image sensor chip, shared memory, and retinal prosthesis chip have been fabricated successfully.

Experimental evaluation of stimulus current generator with Laplacian edge-enhancement for 3-D stacked retinal prosthesis chip

Abstract: To restore visual sensation of blind patients suffering from age-related macular degeneration (AMD) and retinitis pigmentosa (RP), we have been developing fully-implantable retinal prosthesis consisting of three dimensional (3-D) stacked retinal prosthesis chip with high density through silicon vias (TSVs), flexible cable, and a stimulus electrode array. Using 3-D integration technology, a photoreceptor chip with more than 1000 pixels can be fabricated in the top layer, and stimulus current generator with various image processing functions can also be fabricated in the bottom layer. In this paper, we presented experimental evaluation results of the stimulus current generator with Laplacian edge-enhancement function. The proposed edge enhancement (EE) function used a four-neighbor Laplacian filter circuit as analog signal processing and was implemented in a 0.18-μm 1P6M CMOS technology. A pixel size including the four-neighbor Laplacian filter circuit was 75 × 75 μm2, and 37 × 37 pixels occupied a very small active circuit area of 3.2 × 3.2 mm2. Experimental results showed the fabricated stimulus current generator completely captured an input image and successfully performed the EE processing for the input image data. Furthermore, total output current from photo-diodes, which became input currents of biphasic pulse generator, was reduced by 87% with the EE circuit. Safer electrical stimulations to the retina cells can be realized with the stimulus current generator with Laplacian EE in the 3-D stacked retinal prosthesis chip.

3-D Sidewall Interconnect Formation Climbing Over Self-Assembled KGDs for Large-Area Heterogeneous Integration

Abstract: Massively parallel chip assembly based on multi-interposer block concept is demonstrated for large-area heterogeneous system integration. The chips are aligned in parallel by liquid surface tension and assembled on the Si interposers through oxide-oxide bonding at room temperature without thermocompression. 3-D Cu sidewall interconnects (the width is approximately $20~\mu \text{m}$ ) climbing over 100- $\mu \text{m}$ -thick self-assembled chips are formed with a spin-on thick photoresist by electroplating. In addition, 3-D Cu interconnects with a width of nearly $10~\mu \text{m}$ are successfully formed across polyimide slopes formed on the sidewall of self-assembled chips. The electrical properties of the 3-D sidewall interconnects are characterized by the daisy chains, resistance distribution, and characteristic fluctuation of CMOS fabricated on the self-assembled chips.

Evaluation of insertion characteristics of less invasive Si optoneural probe with embedded optical fiber

Abstract: A less invasive Si optoneural probe with an embedded optical fiber was proposed and successfully fabricated. The diameter of the optical fiber was completely controlled by hydrogen fluoride etching, and the thinned optical fiber can propagate light without any leakage. This optical fiber was embedded in a trench formed inside a probe shank, which causes less damage to tissues. In addition, it was confirmed that the optical fiber embedded in the probe shank successfully irradiated light to optically stimulate gene transfected neurons. The electrochemical impedance of the probe did not change despite the light irradiation. Furthermore, probe insertion characteristics were evaluated in detail and less invasive insertion was clearly indicated for the Si optoneural probe with the embedded optical fiber compared with conventional optical neural probes. This neural probe with the embedded optical fiber can be used as a simple and easy tool for optogenetics and brain science.

Ultrawide range square wave impedance analysis circuit with ultra-slow ring-oscillator using gate-induced drain-leakage current

Abstract: This paper presents area efficient and ultrawide range square wave impedance analysis circuit for biomedical applications. By using a gate-induced drain-leakage current (GIDL), we designed an ultralow current generation circuit which is a key component of the impedance measurement circuit and a GIDL-controlled oscillator operating at ultralow frequency. In addition, the area of the impedance measurement circuit becomes remarkably small due to square waveform current. All impedance measurement circuits are fabricated with a 0.18μm 1P6M standard CMOS technology and occupy 0.43mm2. As results, the proposed GIDL-controlled oscillator circuit successfully oscillated at ultralow frequency of 3.1Hz, and the impedance measurement circuit completely outputs square waveforms with a current amplitude of 50pA. The proposed circuit can measure impedance ranges from 100Ω to 100MΩ.

Data acquisition method, data acquisition device, and recording medium

Abstract: A non-transitory computer-readable recording medium stores a data acquisition program that causes a computer to execute a process including: extracting first data and second data that are separated from each other by a predetermined tag or symbol, from a document written in HTML; displaying the extracted first data and the extracted second data in an associated manner; and specifying a position of a tag included in the document on a hierarchical structure with respect to the first data or the second data in the document to allow registration of the position on the hierarchical structure, upon detecting that the displayed first data or the displayed second data is selected.

Information acquisition method, and information acquisition device

Abstract: An information acquisition method includes: acquiring a specific piece of data using information for specifying a position of the specific piece of data in a document of a certain site by referring to a storage that stores therein information for specifying the position of the specific piece of data in the document of the certain site and information for specifying a position of another piece of data having a predetermined relation to the specific piece of data in the document, by a processor; and acquiring the other piece of data using the position of the other piece of data related to the specific piece of data in the document by referring to the storage, and acquiring data having the predetermined relation to the other piece of data using the acquired other piece of data, by the processor.

Evaluation of Stimulus Current Generator with Laplacian Edge-Enhancement for 3-D Stacked Retinal Prosthesis Chip

Abstract: To restore visual sensation of blind patients suffering from age-related macular degeneration (AMD) and retinitis pigmentosa (RP), we have been developing fully-implantable retinal prosthesis consisting of three dimensional (3-D) stacked retinal prosthesis chip with high density through silicon vias (TSVs), flexible cable, and a stimulus electrode array. Using 3-D integration technology, a photoreceptor chip with more than 1000 pixels can be fabricated in the top layer, and stimulus current generator with various image processing functions can also be fabricated in the bottom layer. In this paper, we presented experimental evaluation results of the stimulus current generator with Laplacian edge-enhancement function. The proposed edge enhancement (EE) function used a four-neighbor Laplacian filter circuit as analog signal processing and was implemented in a 0.18-μm 1P6M CMOS technology. A pixel size including the four-neighbor Laplacian filter circuit was 75 × 75 μm2, and 37 × 37 pixels occupied a very small active circuit area of 3.2 × 3.2 mm2. Experimental results showed the fabricated stimulus current generator completely captured an input image and successfully performed the EE processing for the input image data. Furthermore, total output current from photo-diodes, which became input currents of biphasic pulse generator, was reduced by 87% with the EE circuit. Safer electrical stimulations to the retina cells can be realized with the stimulus current generator with Laplacian EE in the 3-D stacked retinal prosthesis chip.

Data acquisition method, data acquisition apparatus, and recording medium

Abstract: A non-transitory computer-readable recording medium storing a data acquisition program that causes a computer to execute a process including: identifying a position of a part to be extracted in a document that is associated with a specific URL and includes structural information of tags, the position being on a hierarchical structure of the tags included in the document, and allowing the position on the hierarchical structure to be registered; and accessing periodically or non-periodically the document associated with the specific URL, and extracting and outputting data corresponding to the registered position on the hierarchical structure of the tags.

Data verification device

Abstract: A data verification device includes a processor configured to: specify, out of a plurality of sites registered as acquisition sources of specific information, reliability of the site from which the information was acquired as the specific information based on storage content of a storage that stores therein the reliability in association with each of the sites; and output the information acquired as the specific information together with the specified reliability.

Development of Si neural probe with piezoresistive force sensor for minimally invasive and precise monitoring of insertion forces

Abstract: A Si neural probe is one of the most important tools for neurophysiology and brain science because of its various functions such as optical stimulation and drug delivery. However, the Si neural probe is not robust compared with a metal tetrode, and could be broken by mechanical stress caused by insertion to the brain. Therefore, the Si neural probe becomes more useful if it has a stress sensor that can measure mechanical forces applied to the probe so as not to be broken. In this paper, we proposed and fabricated the Si neural probe with a piezoresistive force sensor for minimally invasive and precise monitoring of insertion forces. The fabricated piezoresistive force sensor accurately measured forces and successfully detected insertion events without buckling or bending in the shank of the Si neural probe. This Si neural probe with a piezoresistive force sensor has become one of the most versatile tools for neurophysiology and brain science.

Tabular data analysis method, tabular data analysis program, and information processing device

Abstract: Provided are a tabular data analysis method, a tabular data analysis program, and an information processing device capable of easily registering tabular data in various formats. The tabular data analysis method includes executing, by a computer (100), a process (131) for determining existence/nonexistence of cells in which data have been input for each row or each column of input tabular data. The tabular data analysis method further includes executing, by the computer (100), a process (132) for extracting a cluster of a plurality of continuous rows or columns where cells in which data have been input exist, as a part relating to one piece of tabular data.

Item name associating process method, item name associating process program, and information processing device

Abstract: Provided are an item name associating process method, an item name associating process program, and an information processing device capable of associating an item name with a standardized vocabulary. The item name associating process method includes the following processes performed by a computer (100). The item name associating process method extracts a plurality of item names from tabular data. Further, the item name associating process method refers to a storage unit in which a plurality of item groups is stored to determine an item group including an item name having a predetermined similarity relationship with each of the plurality of extracted item names. With respect to an item name among the plurality of item names for which a positive determination result has been obtained, the item name associating process method selects the item name having the predetermined similarity relationship as the object for association. With respect to an item name for which a negative determination result has been obtained, the item name associating process method presents an item group determined to include the item name having the predetermined similarity relationship with another item name as an association candidate.