Showing papers by "Tetsu Tanaka published in 2018"

Prognostic Impact of Computed Tomography-Derived Abdominal Fat Area on Transcatheter Aortic Valve Implantation

Abstract: Background Obesity has previously been identified as an indicator of good prognosis in patients undergoing transcatheter aortic valve implantation (TAVI), an association known as the "obesity paradox". We investigated whether abdominal total fat area (TFA), visceral fat area (VFA), or subcutaneous fat area (SFA) are prognostic indicators of long-term clinical outcome in patients undergoing TAVI. Methods and Results: We retrospectively analyzed 100 consecutive patients who underwent TAVI between December 2013 and April 2017. TFA, VFA, and SFA were measured from routine pre-procedural computed tomography (CT). Patients were divided into 2 groups according to median TFA, VFA, or SFA, and we investigated the association of abdominal fat area with adverse clinical events, including all-cause death and re-hospitalization due to worsening heart failure. At a median follow-up of 665 days, patients with higher SFA had significantly lower incidence of the composite outcome and all-cause death compared with patients with lower SFA (15.0% vs. 37.7%, P=0.025; and 8.9% vs. 23.7%, P=0.047, respectively). In contrast, patients with higher TFA or VFA did not show significant reduction in the incidences of the composite outcome or all-cause mortality. Conclusions CT-derived SFA had prognostic value in patients undergoing TAVI.

Charge-Trap-Free Polymer-Liner Through-Silicon Vias for Reliability Improvement of 3D ICs

Abstract: Through-silicon-via (TSV) with polymer liner has attracted considerable attention because a polymer liner has low dielectric constant and good step coverage along the TSV surface, and it can suppress the TSV-induced stress. A polyimide (PI) is used as the polymer liner of TSV. However, there is a modulation of the parasitic capacitance present between TSV metal and Si substrate due to its high polar character. Therefore, in this paper, we propose the deployment of benzocyclobutene (BCB) and polybenzoxazole (PBO) which consists of no-polar groups as the polymer-liner material of TSV for minimizing the capacitance modulation. In this study, a metal-insulator-semiconductor capacitor with blind TSV structures with PI, BCB or PBO liners were fabricated and evaluated. In the case of BCB and PBO liners, remarkable hysteresis suppressions of the C-V curves was observed as compared to that of the PI liner. These results indicate that polar character is one of the most important characters for suppression of the capacitance modulation around TSVs and the detrapped-charge-induced signal noise. Then, BCB and PBO is a promising liner material of TSV for realizing highperformance and high-reliability three-dimensional stacked ICs.

Development of integrated photoplethysmographic recording circuit for trans-nail pulse-wave monitoring system

Abstract: Health monitoring and self-management have become increasingly more important because of health awareness improvement, the aging of population, and other reasons. In general, pulse waves are among the most useful physiological signals that can be used to calculate several parameters such as heart rate and blood pressure for health monitoring and self-management. To realize an automatic and real-time pulse-wave monitoring system that can be used in daily life, we have proposed a trans-nail pulse-wave monitoring system that was placed on the fingernail to detect photoplethysmographic (PPG) signals as pulse waves. In this study, we designed a PPG recording circuit that was composed of a 600 × 600 µm2 photodiode (PD), an LED driver with pulse wave modulation (PWM) and a low-frequency ring oscillator (RING), and a PPG signal readout circuit. The proposed circuit had a very small area of 2.2 × 1.1 mm2 designed with 0.18 µm CMOS technology. The proposed circuit was used to detect pulse waves on the human fingernail in both the reflection and transmission modes. Electrical characteristics of the prototype system were evaluated precisely and PPG waveforms were obtained successfully.

Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

Abstract: Charge-trapping memory requires the increase of bit density per cell and a larger memory window for lower-power operation. A tunnel field-effect transistor (TFET) can achieve to increase the bit density per cell owing to its steep subthreshold slope. In addition, a TFET structure has an asymmetric structure, which is promising for achieving a larger memory window. A TFET with the N-type gate shows a higher electric field between the P-type source and the N-type gate edge than the conventional FET structure. This high electric field enables large amounts of charges to be injected into the charge storage layer. In this study, we fabricated silicon–oxide–nitride–oxide–semiconductor (SONOS) memory devices with the TFET structure and observed a steep subthreshold slope and a larger memory window.

The Effect of Mechanical Stress on Cell Characteristics in MONOS Structures

Abstract: We investigated the impact of mechanical stress on the cell characteristics of metal–oxide–nitride–oxide–semiconductor (MONOS) structures through experimental observations based on a curvature method for residual stress extraction and an analysis of the interface state. Residual stress induced on a substrate was observed to change from compressive to tensile depending on the tungsten process conditions; a high interface trap density was extracted under a high compressive stress environment based on a silicon bonding model. These interface trap densities were suggested as being attributable to a critical factor weakening the leakage characteristics of the MONOS structure. Besides, interface traps interrupted electron tunneling due to unintended charge trapping at the interface, which deteriorated memory characteristics indicated by a reduction in trap density. These results experimentally supported the effects of mechanical stress on device characteristics and reliability, which could be a straightforward way toward understanding the impact of stress for improved future flash memory applications.

Study of Al-doped ZnO transparent stimulus electrode for fully implantable retinal prosthesis with three-dimensionally stacked retinal prosthesis chip

Abstract: To realize a three-dimensionally (3D) stacked retinal prosthesis chip having a large stimulus electrode area and a large photodiode area, the fundamental properties of an Al-doped ZnO transparent stimulus electrode were investigated in detail. The test samples were fabricated, and thin film property and stimulus electrode characteristics were also evaluated using several methods. It was clearly observed that both the crystallinity and transmittances of an Al-doped ZnO thin film were dependent on the substrate temperature during thin-film formation. A better crystallinity and a transmittance of more than 85% in the visible range were achieved for the Al-doped ZnO thin film with a substrate temperature of 200 °C. Furthermore, good electrochemical impedance characteristics and adequate charge injection capacity (CIC) values of 0.07 mC/cm2 were obtained to elicit visual sensations. Consequently, Al-doped ZnO has the possibility of becoming the transparent stimulus electrode for a 3D stacked retinal prosthesis chip.

Continuous Peripheral Blood Pressure Measurement with ECG and PPG Signals at Fingertips

Abstract: A good habit of measuring blood pressure (BP) daily is helpful for us to stay healthy or to monitor hypertensive conditions. However, the conventional method of measuring BP using a pressure cuff has many weaknesses. In order to eliminate the use of this pressure cuff, we proposed a system using the pulse arrival time (PAT) to measure BP. This PAT can be measured using time difference between the R-peaks of electrocardiogram (ECG) and photoplethysmography (PPG) signals. In our system, we obtained these two signals by using our self-designed ECG and PPG sensors. Our sensors were fabricated in 0.18 μm CMOS technology with a small recording area of about 2.53 mm2and 6.25 mm2, respectively. Our ECG sensor has variable amplifying gains and can achieve a total maximum gain of 60 dB. Besides that, it has a high pass filter with wide cutoff frequencies between 0.1-200 Hz, and low pass filter with cutoff frequencies of 0.2-10 kHz. The design of our ECG circuit allows us to obtain the ECG signals using fingertips and without using a ground electrode. This compact system has the potential to become a wireless wearable in the future. The measured PAT was fitted into a mathematical model and cuff-less BP readings were obtained. A plot of reference BP using oscillometric cuff and cuff-less BP showed a good correlation of r = 0.83 for systolic blood pressure (SBP). The SBP and diastolic blood pressure (DBP) mean absolute difference for the system are 6.75 mmHg and 6.08 mmHg respectively, which fairly passed the strict standard set by IEEE. In the future, our system will be compared with the use of sphygmomanometer, which is the gold standard, to further evaluate its accuracies.

Advanced Tape Expansion/Assembly Technology for FOWLP and Micro-LED Display

Abstract: This paper describes advanced assembly technologies based on a new tape expansion technique with a selective UV irradiation method for the application of FOWLP (Fan-Out Wafer-Level Packaging) with millimeter-scale dies and micro-LED display with several tens of micrometer-scaled dielets. The assembly technologies allow us to uniformly expand expansion tapes in all direction and array the dies/dielets at the regular pitches desired for their products. We demonstrate the uniform expansion of an expansion tape with 3-mm-square Si dies and 50-μm-square Si dielets using selectively irradiated UV light through a photomask.

Challenges in 3D Integration

Abstract: Introduction Three-dimensional (3D) LSIs using TSVs are indispensable to achieve high performance and low power LSIs with smaller form factor. A wafer-to-wafer (WtW) technology is suitable for stacking chips with high production yield such as DRAM since the overall yield after stacking rapidly decreases as the number of stacking layers increases. The chipto-wafer (CtW) is suitable for stacking known good dies (KGDs). In addition, chips with different size which are fabricated using different process technologies can be stacked in the CtW technology. The inherent problem in the CtW technology, however, is low production throughput. To solve these problems, we have proposed a new 3D heterogeneous integration technology called a super-chip technology using self-assembly and electrostatic (SAE) bonding method [4]. Heterogeneous Integration and 3D Superchip Super-chip technology makes possible to merge different kinds of technologies such as packaging, MEMS, photonics and so on as shown in Fig.1. A new self-assembly and electrostatic (SAE) bonding method is employed in this super-chip technology for stacking various kinds of chips with different chip size and chip thickness which are fabricated using different process technologies. A number of chips are simultaneously aligned and bonded with high alignment accuracy of less than 0.5μm by making use of the surface tension of liquid and electrostatic force. SAE (Self-Assembly and Electrostatic) Bonding KGDs are directly carried from a tested wafer to an electrostatic multichip carrier (e-carrier), and then are released onto water droplets provided on hydrophilic bonding regions formed on the e-carrier. Thus many KGDs are precisely self-assembled on the e-carrier. After self-assembly, the KGDs are temporarily bonded to the ecarrier by electrical charging with high DC voltage. Then, the e-carrier with the KGDs is aligned and temporarily bonded to the corresponding support wafer on which a temporary adhesive is coated . In a multichip-to-wafer (MCtW) technology using Self-Assembly and Electrostatic (SAE) bonding, the temporarily bonded many KGDs are readily debonded from the e-carrier and transferred to the support wafer by discharging the voltage. The subsequent processes are resin molding, multichip thinning, TSV/microbump formation, and second multichip transfer from the support wafer to the corresponding target LSI wafer. The temporary adhesive used in this process has high thermal stability whereas glued chips can be easily removed from the support wafer after TSV formation. By repeating the sequence, we can obtain 3D stacked thin chips with TSVs. Fabrication of Heterogeneous 3D LSI We have been developing various kinds of heterogeneous 3D LSIs using 3D super-chip technology. A 3Dstacked image sensor chip is one example of these heterogeneous 3D LSIs. Our 3D-stacked image sensor chip is composed of CMOS image sensor (CIS) layer, correlated double sampling circuit (CDS) layer, and analogto-digital converter (ADC) array layer. One image frame with 320×240 pixels is divided into 20×15 image processing blocks. Each block is composed of 256 CIS pixel circuits, one CDS circuit, and one ADC circuit which are electrically connected TSVs. The CIS chip was fabricated using 0.18μm front-side illumination CMOS image sensor technology. Each pixel is designed with 10μm×10μm size and one image processing block has 255 pixels and one Cu TSV with the diameter of 5μm. The CDS chip and ADC chip were fabricated using 0.18μm CMOS technology and 90-nm CMOS technology, respectively. Each chip has 5×5mm 2 size. We stacked these chips by a novel chip-based heterogeneous integration technology. The comercially available 2D chips are processed and integrated in chip-level. First of all, before stacking three kinds of chips, Cu/Sn microbumps are formed on the surface of each chip. Each functional chip with Cu/Sn microbumps is glue-bonded temporally to a supporting glass substrate and thinned down to 40μm thickness. Via holes with 5μm dia. are etched from the backside of Si substrate. The dielectric liner at the bottom of hole is etched by dry etching. Then holes are filled with Cu by elctroplating. Next Cu and Sn electroplating are used to form backside Cu/Sn microbumps. By repeating these processes, we fabricated 3D-stacked image sensor. The bird's-eye view and crosssectional image of the fabricated 3D-stacked image sensor are shown in Figs. 2 and 3 . We have confirmed basic function of this 3D-stacked image sensor chip.

Self-Assembly Technologies for FlexTrate™

Abstract: We have developed new flexible hybrid electronics (FHE) systems called FlexTrateTM that is high-performance and scalable flexible substrates embedding heterogeneous inorganic monocrystalline semiconductor dielets. In this work, a modified die-first FOWLP technology with surface tension-driven multichip self-assembly is used for the fabrication of FlexTrateTM. The detailed self-assembly for the FlexTrateTM application is described to precisely and highly integrate heterogeneous dielets embedded in PDMS as a flexible substrate in wafer-level processing.

TSV liner dielectric technology with spin-on low-k polymer

Abstract: In this paper, a BCB (benzocyclobutene) resin is employed as a spin-on low-k polymer for TSV liner dielectrics. The BCB is perfectly covered on the sidewall of deep Si holes with a diameter of 8 μm and depth of 40 μm (aspect ratio: 5). The step coverage of the BCB is high and controllable by conditioning the spin rotation speed, spin-coating time, and deforming pressure to eliminate bubbles formed in the deep Si holes prior to spin-coating. Cu-TSVs with the BCB liner dielectric are successfully formed by the subsequent electro-less plated and electroplated Cu technologies. This cost-effective spin-on BCB technology will be applied to via-last TSV fabrication at low temperature below 250 C to give low-capacitance TSVs.

ST-Segment Elevation Myocardial Infarction Related to Variable Calcified Lesions in Saphenous Vein Graft 33 Years After Coronary Artery Bypass Grafting.

Abstract: A 94-year-old woman presented with anterior ST-segment elevation myocardial infarction. She underwent coronary artery bypass grafting with implantation of a saphenous vein graft (SVG) from the aorta to the left anterior descending coronary artery 33 years ago. Emergency coronary angiography revealed

Process Integration for FlexTrate TM

Abstract: We fabricate FlexTrateTM that is highly integrated bendable and/or rollable electronic systems in which various Si and/or III–V chips are embedded in elastomers and interconnected at the wafer level. This paper describes the process integration of the FlexTrateTM using massively parallel capillary self-assembly and a new single stress buffer layer technologies to form fine-pitch interconnection between the embedded neighboring chips and characterize the electrical/mechanical properties.

Efficacy of Pericardial Drainage in Annular Rupture and Periaortic Hematoma After Transcatheter Aortic Valve Replacement.

Abstract: Received January 30, 2018; revised manuscript received May 1, 2018; accepted May 17, 2018; released online June 22, 2018 Time for primary review: 21 days Division of Cardiology (T.T., K.Y., T.O., K.S., K.T.), Division of Cardiovascular Surgery (A.O., S.M.), Division of Anesthesia (M.Y.), Mitsui Memorial Hospital, Tokyo, Japan Mailing address: Kazuyuki Yahagi, MD, Division of Cardiology, Mitsui Memorial Hospital, 1 Kanda-Izumi-cho, Chiyoda-ku, Tokyo 101-8643, Japan. E-mail: yyahakazu@gmail.com ISSN-1346-9843 All rights are reserved to the Japanese Circulation Society. For permissions, please e-mail: cj@j-circ.or.jp Efficacy of Pericardial Drainage in Annular Rupture and Periaortic Hematoma After Transcatheter Aortic Valve Replacement

Development of 3D-Stacked Multi-Shank Si Neural Probe Array (1) - Fabrication of Embedded Multiple Optical Fibers in Multi-Shank -

Abstract: Introduction Many researches have been developing medical treatments for brain diseases, analyzing brain functions, and so on. Then, various kinds of neural probes were developed and used for recording neuronal action potentials and other brain activities. Especially, a Si neural probe is one of the most important tools to analyze brain functions [1]. In this paper, we proposed a 3D-stacked Si neural probe array with multiple optical fibers for multiple optical stimulation and high density electical recording of neurons, as shown in Fig. 1. Direct optical stimulation is an effective method to realize a precise stimulation of neurons. Optical stimulation methods are roughlly classified into two categolies. One is stimulation with visible light. Another is stimulation with infrared light. In the case of visible light stimulation, the gene transfer technology was used, and neurons expressed a light sensitive channel protein such as Channelrhodopsin-2 (ChR2). The analyzing method using a light sensitive channel protein is called optogenetics. On the other hand, infrared neural stimulation has atracted much attentions for direct activation of nerves via the transient heating of water without any need for tissue modification. There are advantages and disadvantaes in both method [2]. Our proposed probe can activate neurons by both visible and infrared lights using optical fiber with external light sources. In addition, our probe has multiple optical stimulation sites and high density recording electrodes owing to 3D-stacking technology. This high density recording electrodes can realize three dimensional recording of neural actions. Fabrication As the Si neural probe was fabricated by micro and nano fabrication technologies used for LSI fabrication, it was possible to realize high density recording sites. First, SiO2 was deposited on both surfaces of the Si wafer [3]. Then, Au wire was formed by sputtering and wet etching. After passivation of the Au wire by SiO2, SiO2 was etched to form the hard mask for the trench etching. The optical fibers are set into this trench. Then, contact holes for the recording sites and I/O pads were formed. After that, the probe shape was formed by deep reactive ion etching (Deep RIE) from back surface of the Si wafer. Then, the probes were sharpened by anisotropic wet etching with TMAH. Finally, the optical fibers with a diameter of 30-um were embedded into the trench formed on the probes, and fixed with a UV curable resin.

Tabular data analysis method, recording medium storing tabular data analysis program, and information processing apparatus

Abstract: A tabular data analysis method includes determining, by a computer, whether a cell having data is present for each row or each column of input tabular data, and extracting, in a case where there is one or more cells having data, a block of rows or columns in which the one or more cells are consecutively included, as a part related to one piece of table data.