Showing papers by "Tetsu Tanaka published in 2020"

7-μm-thick NCF technology with low-height solder microbump bonding for 3D integration

Abstract: High-density interconnections are highly required for 3D IC such as FPGA and image sensor applications. Fine-pitch interconnects using conventional solder microbumps are still required. To meet this requirements, low-height Cu/Sn microbumps are evaluated in this study. The thermal compression bonding with the low-height solder microbumps makes it challenging to fulfill high-viscous capillary underfill (CUF) into extremely small gaps between the chips stacked in layers. Here, we demonstrate to apply a 7-μm-thick non-conductive film (NCF) to flip-chip bonding with the low-height solder microbumps. Compared with a CUF, the electrical characterization such as electromigration (EM) and leakage current of microbump daisy chains with the ultra-thin NCF was investigated with temperature cycle test (TCT) and unbiased HAST.

Significant Die-Shift Reduction and μ LED Integration Based on Die-First Fan-Out Wafer-Level Packaging for Flexible Hybrid Electronics

Abstract: Typical die shift is beyond several tens micrometers or more, which is a serious problem on advanced fan-out wafer-level packaging (FOWLP), to give inevitable misalignment errors in the subsequent photolithography processes for fine-pitch redistributed wiring layer (RDL) formation. In particular, this problem is expected to grow all the more serious in chiplets and tiny dies less than 1 mm in a side. In this work, the use of an anchoring layer is proposed to fix these dies/chiplets on a double-side laminate thermo-release tape and drastically reduce the die shift. In addition, an on-nail photoplethysmogram (PPG) sensor module as a part of flexible hybrid electronics (FHE) is integrated with $\mu $ LED ( $270\,\,\mu \text{m}\,\,\times 270\,\,\mu \text{m}$ ) based on a die-first FOWLP methodology using a biocompatible polydimethylsiloxane (PDMS) mold resin for real-time monitoring pulse wave and percutaneous oxygen saturation (SpO2). The repeated bendability of fan-out Au wirings formed on the PDMS and the current–voltage ( $I$ – $V$ ) behavior of the $\mu $ LED before and after die embedment in the PDMS is characterized.

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Abstract: Spiking neural networks (SNNs) have attracted considerable attention as next-generation neural networks. As SNNs consist of devices that have spike-timing-dependent plasticity (STDP) characteristics, STDP is one of the critical characteristics we need to consider to implement an SNN. In this study, we generated the STDP of a biological synapse with non-volatile tunnel-field-effect-transistor (tunnel FET) memory that has a charge-storage layer and a tunnel FET structure. Tunnel FET is a promising structure to reduce the operation voltage owing to its steep sub-threshold slope. Therefore, the non-volatile tunnel-FET memory we propose enables the implementation of low-operation-voltage SNNs. This article reports the ${I-V}$ , programming, and both symmetric and asymmetric STDP characteristics of a non-volatile tunnel-FET memory with p-channel-MOS-like operation.

Low-temperature multichip-to-wafer 3D integration based on via-last TSV with OER-TEOS-CVD and microbump bonding without solder extrusion

Abstract: This paper deals with multichip-to-wafer (MC2W) 3D stacking technologies based on via-last TSV integration. In this work, we verify the effectiveness of room-temperature CVD named OER (Ozone-Ethylene Radical generation)-TEOS-CVD® to deposit a TSV liner SiO 2 layer. The film quality including dielectric constants is evaluated alternative to plasma-enhanced (PE)-TEOS-CVD SiO 2 . In addition, solid-solid inter-diffusion bonding of 3-μm-thick Sn with 0.5-μm-thick Au is demonstrated to achieve multiple multichip bonding for retinal prosthesis system fabrication with a 3D artificial retina chip. Low-temperature bonding at 190°C is realized by the Au/Sn metallurgy. Good bondability is also obtained with the Au electrodes preliminarily exposed at high temperature. There are no Sn microbump extrusion, which is highly expected to be used for 3D-ICs with fine-pitch solder microbump interconnection.

RDL-first Flexible FOWLP Technology with Dielets Embedded in Hydrogel

Abstract: A new flexible hybrid electronics (FHE) methodology using advanced RDL-first fan-out wafer-level packaging (FOWLP) technologies with dielets and hydrogel substrates is proposed. Hydrogels mainly consisting of water have excellent biocompatibility, high adaptability, and substance permeability, and they are expected for biomedical applications. In this work, we integrate Si LSI and mini-LED dielets in a hydrogel substrate on which fine-feature Au interconnections are formed in wafer-level processing. We characterize their electrical properties of the embedded dielets for biomedical applications.

Corroborative Autopsy Findings for Current Concerns After Implantation of Self-Expandable Transcatheter Heart Valve.

Abstract: An 85-year-old man with chronic obstructive pulmonary disease was referred to our institution to treat congestive heart failure caused by severe aortic valve stenosis (AS). Pre-procedural computed tomography assessments showed type 1 functional bicuspid AS with fused right and left coronary cusps ([

Development of Non-Volatile Tunnel-FET Memory as a Synaptic Device for Low-Power Spiking Neural Networks

Abstract: Spiking neural network (SNN) has attracted much attention as next-generation neural networks. To realize SNN, the spike-timing-dependent plasticity (STDP) is one of the critical characteristics. In this study, we demonstrated the STDP of a biological synapse with non-volatile tunnel-field-effect transistor (FET) memory. Tunnel FET is a promising candidate to reduce the power consumption owing to the steep subthreshold characteristics. Therefore, non-volatile tunnel-FET memory we proposed has the possibility to realize low-power SNN. This paper reported the current-voltage characteristics, the memory window., and the STDP characteristics of the nonvolatile tunnel-FET memory.