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Tetsu Tanaka

Researcher at Tohoku University

Publications -  423
Citations -  11239

Tetsu Tanaka is an academic researcher from Tohoku University. The author has contributed to research in topics: Wafer & Chip. The author has an hindex of 38, co-authored 406 publications receiving 10375 citations. Previous affiliations of Tetsu Tanaka include NTT DoCoMo & Tokyo Medical and Dental University.

Papers
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Proceedings ArticleDOI

3D integration technology for 3D stacked retinal chip

TL;DR: To recover visual sensation of blind patients, a novel three dimensionally stacked retinal prosthesis chip in which several LSI chips such as consisting of photodetector, signal processing circuit and stimulus current generator are vertically stacked and electrically connected using 3D integration technology is proposed.
Proceedings ArticleDOI

Ultrafast low-power operation of p/sup +/-n/sup +/ double-gate SOI MOSFETs

TL;DR: In this article, a double-gate SOI MOSFET with a p/sup +/-n/sup +/ double gate was constructed and the authors obtained an inverter delay of 43 ps at 1 V and 27 ps at 2 V.
Journal ArticleDOI

Leaflet Configuration and Residual Tricuspid Regurgitation After Transcatheter Edge-to-Edge Tricuspid Repair

TL;DR: In this paper, the tricuspid leaflet morphologies were imaged using 2-dimensional and 3-dimensional transesophageal echocardiography to assess the anatomical leaflet variation and investigate its impact on the procedural outcome in patients undergoing transcatheter edge-to-edge tricusid repair.
Journal ArticleDOI

Degradation of Memory Retention Characteristics in DRAM Chip by Si Thinning for 3-D Integration

TL;DR: In this paper, a DRAM chip of 200-μm thickness is bonded to a Si interposer and thinned down to 50/40/30/20/20μm.
Journal ArticleDOI

Analytical Models for Symmetric Thin-Film Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistors

TL;DR: In this article, the authors derived analytical models for the currentvoltage characteristics of double-gate silicon-on-insulator metal-oxide-semiconductor-field effect transistors.