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Tetsu Tanaka

Researcher at Tohoku University

Publications -  423
Citations -  11239

Tetsu Tanaka is an academic researcher from Tohoku University. The author has contributed to research in topics: Wafer & Chip. The author has an hindex of 38, co-authored 406 publications receiving 10375 citations. Previous affiliations of Tetsu Tanaka include NTT DoCoMo & Tokyo Medical and Dental University.

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Journal ArticleDOI

Barrier Properties of CVD Mn Oxide Layer to Cu Diffusion for 3-D TSV

TL;DR: In this article, the effect of oxide substrate on the barrier property of a planar Mn oxide was evaluated by XPS method, and a vertical Mn oxide layer with 20-nm thickness formed on P-TEOS oxide liner in TSV showed better barrier property, when compared with the sputtered Ta barrier layer, up to 400°C annealing condition.
Journal ArticleDOI

Low-Resistance Cu-Sn Electroplated–Evaporated Microbumps for 3D Chip Stacking

TL;DR: In this article, low-resistance copper-tin (Cu-Sn) microbumps, with sizes varying from 5 μm × 5 µm to 20μm × 20 µm and formed by electroplating-evaporation bumping (EEB) technology for three-dimensional integration of large-scale integrated chips, have been evaluated for their microstructure and electrical resistance.
Journal ArticleDOI

Investigation of Local Bending Stress Effect on Complementary Metal–Oxide–Semiconductor Characteristics in Thinned Si Chip for Chip-to-Wafer Three-Dimensional Integration

TL;DR: In this paper, the impact of local bending stress on the performance of a complementary metal-oxide-semiconductor (CMOS) circuit fabricated in a thinned Si chip was investigated.
Proceedings ArticleDOI

Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system

TL;DR: The chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor that combines through-Si vias and metal micro-bumps formed in chip-level before stacking.