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Tetsu Tanaka

Researcher at Tohoku University

Publications -  423
Citations -  11239

Tetsu Tanaka is an academic researcher from Tohoku University. The author has contributed to research in topics: Wafer & Chip. The author has an hindex of 38, co-authored 406 publications receiving 10375 citations. Previous affiliations of Tetsu Tanaka include NTT DoCoMo & Tokyo Medical and Dental University.

Papers
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Journal ArticleDOI

Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

TL;DR: In this paper, the effect of noise propagation from a digital circuit on an analog circuit was evaluated using an actual mixed-signal 3D-IC, with a ring-oscillator as a noise source.
Patent

Chip support substrate, chip support method, three-dimensional integrated circuit, assembly device, and fabrication method of three-dimensional integrated circuit

TL;DR: In this article, a chip support substrate including a lyophilic region 4 that is formed on the substrate and that absorbs a chip 3 A, and an electrode 6 that was formed on a substrate and in the lyphilic region and that generated electrostatic force in the chip, was described.
Journal ArticleDOI

Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration

TL;DR: In this paper, a self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3D integration.
Journal ArticleDOI

Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice

TL;DR: In this article, a 50-μm-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction.
Proceedings ArticleDOI

A study on millisecond annealing (MSA) induced layout dependence for flash lamp annealing (FLA) and laser spike annealing (LSA) in multiple MSA scheme with 45 nm high-performance technology

TL;DR: In this article, the dependence of temperature uniformity dufing millisecond annealing (MSA) on the pattern density and its effect on device characteristics and static random access memory (SRAM) yields with 45-nm node technology was investigated.