Thejas Kempanna

TL;DR: The design and implementation of an 80-kb logic-embedded non-volatile multi-time programmable memory (MTPM) with no added process complexity is described and high-temperature stress results show a projected data retention of 10 years at 125 °C.

TL;DR: An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity.

TL;DR: In this paper, a memory cell includes a pair of a first transistor and a second transistor providing a differential signal output, and a feedback circuit receives one of: a first signal or a second signal of the differential signals, and generates, in response, a feedback signal which is simultaneously applied to bias each current source load transistor in each the first and second circuit legs to amplify a voltage differential between the differential signal outputs.

TL;DR: In this paper, the memory includes a first device of the cell array which is connected to a bitline and a node and controlled by a word line, and a second device consisting of a third device connecting to a source line and the node and controlling by the word line and a fourth device connecting between the source and node, and the third device isolates and floats the node such that a voltage level of a gate to source of the first device is clamped down by the fourth device to around zero volts.

TL;DR: In this paper, the authors present methods and test structures for an intermediate metal level of an integrated circuit (IC), which is one of a plurality of metal levels in the IC structure other than a capping metal level.