Thiam Beng Lim

Bio: Thiam Beng Lim is an academic researcher from National University of Singapore. The author has contributed to research in topics: Integrated circuit packaging & Polyimide. The author has an hindex of 12, co-authored 16 publications receiving 486 citations. Previous affiliations of Thiam Beng Lim include University of Sydney.

Moisture diffusion and vapour pressure modeling of IC packaging

Abstract: A new physical quantity-wetness fraction-has been introduced to overcome the concentration discontinuity in the application of Fick's diffusion equation to multi-material systems such as in plastic IC packaging. This enables the use of commercial thermal diffusion software to model the transient moisture diffusion phenomenon in IC packaging. More significantly, the wetness fraction provides a simple means of computing the vapour pressure in a delaminated region within an IC package when it is heated up to 230/spl deg/C during reflow solder. The approach was bench marked against published works and found to corroborate remarkbly well despite its simplicity.

IC packaging lead frame for reducing chip stress and deformation

Abstract: The present invention relates to a lead frame design for IC packaging to reduce chip stress and deformation and to improve mold filling. The die-pad is split into several sections which are jointed together by flexible expansion joints. The split die-pad allows relative motion between the pad and the chip during die attach cure. It also breaks down the total die pad area (and length) that is rigidly attached to the chip into smaller sections. These two factors reduce the magnitude of coefficient-of-thermal expansion (CTE) mismatch and out of plane deformation of the assembly, resulting in lower chip stress and deformation and improved package moldability.

Method for forming a highly reliable and planar ball grid array package

Abstract: The invention is directed to a BGA package and method for making a BGA package in which warpage, delamination and package cracking are reduced. The inventive BGA package has a die attached to one surface of a substrate. The substrate may terminate at its opposite surface in an array of connection ports which is an integral part of the substrate. Alternatively, the array of connection ports is attached to the opposite surface of the substrate. The connection ports may be attach pads attached to the opposite surface of the substrate and solder balls or metal bumps attached to the attach pads. A matrix of molding compound fully encapsulates the substrate, die and the array of connection ports. The matrix molding compound is then ground to provide a flat surface and to expose portions of the connection ports. Another array of connection ports, such as an array of solder balls or metal bumps, may be attached to the existing array of connection ports. In another embodiment, retracting pins are positioned over the solder attach pads. The mold compound fully encapsulates the substrate, die, solder attach pads and portions of the retracting pins. Removing the retracting pins, after the encapsulation, exposes portions of the solder attach pads so that solder balls or metal bumps are attached to the exposed portions of the solder attach pads.

Advances in Vapor Pressure Modeling for Electronic Packaging

Abstract: Two advanced techniques have been developed for modeling vapor pressure within the plastic IC packages during solder reflow. The first involves the extension of the "wetness" technique to delamination along multimaterial interface and during dynamic solder reflow. Despite its simplicity, this technique is capable of offering reliable and accurate prediction for packages with high flexural rigidity. For packages with low flexural rigidity, the new "decoupling" technique that integrates thermodynamics, moisture diffusion, and structural analysis into a unified procedure has been shown to be more useful. The rigorous technique has been validated on both leadframe-based as well as laminate-based packages. With high accuracy and computational efficiency, these dynamic modeling tools will be valuable for optimization of package construction, materials, and solder reflow profile against popcorn cracking for both SnPb and Pb-free solders

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Packaging of integrated circuits and vertical integration

Abstract: A first level packaging wafer (110) is made of a semiconductor or insulating material. The bumps (150B) on the wafer (110) are made using vertical integration technology, without solder or electroplating. More particularly, vias (160) are etched part way into a first surface of the substrate (140). Metal (150) is deposited into the vias (160). Then the substrate (140) is blanket-etched from the back side (110B) until the metal (150) is exposed and protrudes from the vias (160) to form suitable bumps (150B). Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.

Low-profile microelectronic package

Abstract: A microelectronic package (10) is formed by placing a lead frame (22) onto an adhesive polyimide tape (38). The lead frame (22) includes a plurality of metallic leads (16) and an opening. An integrated circuit die (12) is positioned onto the molding support (38) within the opening such that a non-active face (32) of the integrated circuit die (12) rests against the molding support (38). Wire leads (18) connect an active face (28) of the integrated circuit die (12) to the metallic leads (16). A plurality of metallic bumps (20) are attached to the metallic leads (16), and a polymeric precursor is dispensed. The precursor embeds the active face (28) of the integrated circuit die (12), the inner surface (19) of the metallic leads (16), the wire leads (18), and the metallic bumps (20). The microelectronic package (10) is then heated to cure the polymeric precursor to form a polymeric body (14). The microelectronic package (10) is then capable of being tested and subsequently attached to a printed circuit board (40) to form a low-profile microelectronic assembly (11).

Surface modification of polymers by grafting

Abstract: Recently a variety of technologies have been proposed for improving surface properties of polymers. Among them is surface grafting of polymers. Although this is a rather new technology, polymer surface grafting offers versatile means for providing existing polymers with new functionalities such as hydrophilicity, adhesion, biocompatibility, conductivity, anti-fogging, anti-fouling, and lubrication. This review article describes various methods of grafting and grafted surface characterizations. Medical and non-medical applications connected with this polymer surface grafting are also presented referring to recent publications.