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Thierry Poiroux
Researcher at University of Grenoble
Publications - 148
Citations - 2789
Thierry Poiroux is an academic researcher from University of Grenoble. The author has contributed to research in topics: MOSFET & Silicon on insulator. The author has an hindex of 27, co-authored 146 publications receiving 2563 citations. Previous affiliations of Thierry Poiroux include French Alternative Energies and Atomic Energy Commission.
Papers
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Journal ArticleDOI
Multi- $V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit
J-P Noel,Olivier Thomas,M.-A. Jaud,Olivier Weber,Thierry Poiroux,C. Fenouillet-Beranger,P. Rivallin,P. Scheiblin,F. Andrieu,M. Vinet,O. Rozeau,Frederic Boeuf,O. Faynot,Amara Amara +13 more
TL;DR: In this article, the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage (VT) platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS) was analyzed.
Proceedings ArticleDOI
Advances, challenges and opportunities in 3D CMOS sequential integration
Perrine Batude,Maud Vinet,Bernard Previtali,Claude Tabone,Cuiqin Xu,J. Mazurier,Olivier Weber,Francois Andrieu,L. Tosti,L. Brevard,Benoit Sklenard,Perceval Coudrain,Shashikanth Bobba,H. Ben Jamaa,P.-E. Gaillardon,A. Pouydebasque,Olivier P. Thomas,C. Le Royer,J.M. Hartmann,Loic Sanchez,L. Baud,V. Carron,Laurent Clavelier,G. De Micheli,Simon Deleonibus,O. Faynot,Thierry Poiroux +26 more
TL;DR: This paper addresses the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer and can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices.
Proceedings ArticleDOI
Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond
O. Faynot,Francois Andrieu,Olivier Weber,Claire Fenouillet-Beranger,Pierre Perreau,J. Mazurier,T. Benoist,O. Rozeau,Thierry Poiroux,Maud Vinet,Laurent Grenouillet,J.-P. Noel,Nicolas Posseme,Sébastien Barnola,François Martin,C. Lapeyre,Mikael Casse,X. Garros,M-A. Jaud,Olivier P. Thomas,G. Cibrario,L. Tosti,L. Brevard,Claude Tabone,P. Gaud,Sylvain Barraud,Thomas Ernst,Simon Deleonibus +27 more
TL;DR: In this article, the main advantages of planar undoped channel Fully depleted SOI devices are discussed and solutions to the Multiple V T challenges and non logic devices (ESD, I/Os) are reported.
Journal ArticleDOI
Bonded planar double-metal-gate NMOS transistors down to 10 nm
Maud Vinet,Thierry Poiroux,Julie Widiez,J. Lolivier,Bernard Previtali,C. Vizioz,B. Guillaumot,Y. Le Tiec,P. Besson,B. Biasse,F. Allain,Mikael Casse,D. Lafond,J.M. Hartmann,Yves Morand,J. Chiaroni,Simon Deleonibus +16 more
TL;DR: In this paper, the first 10-nm-gate-length DG MOS transistors with metal gates were processed, which exhibited excellent short-channel effects control and high-performance characteristics.
Proceedings ArticleDOI
Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond
Francois Andrieu,Olivier Weber,J. Mazurier,Olivier P. Thomas,J.-P. Noel,Claire Fenouillet-Beranger,J-P. Mazellier,Pierre Perreau,Thierry Poiroux,Yves Morand,T. Morel,S. Allegret,Virginie Loup,Sébastien Barnola,François Martin,J.-F. Damlencourt,I. Servin,M. Casse,X. Garros,O. Rozeau,M-A. Jaud,G. Cibrario,J. Cluzel,Alain Toffoli,F. Allain,R. Kies,D. Lafond,Vincent Delaye,Claude Tabone,L. Tosti,L. Brevard,P. Gaud,Vamsi Paruchuri,Konstantin Bourdelle,Walter Schwarzenbach,O. Bonnin,By. Nguyen,Bruce B. Doris,Frederic Boeuf,Thomas Skotnicki,O. Faynot +40 more
TL;DR: In this paper, the authors used a single mid-gap gate stack to produce 6T-SRAM cells with good characteristics down to V DD = 0.5V supply voltage and with excellent SNM dispersion across the wafer.