Thomas A. DeMassa

Bio: Thomas A. DeMassa is an academic researcher. The author has contributed to research in topics: Depletion-load NMOS logic & Inverter. The author has an hindex of 1, co-authored 2 publications receiving 641 citations.

Digital Integrated Circuits

Abstract: Partial table of contents: Properties and Definitions of Digital ICS. Diodes. Bipolar Junction Transistors. Diode-Transistor Logic (DTL). Schottky Transistor-Transistor (STTL). Other TTL Gates. Basic Emitter-Coupled Logic (ECL). MECL III and ECL 10K. Other ECL Gates. Introduction to MOS Digital Circuits. Resistor Loaded NMOS Inverter. Enhancement-Depletion Loaded NMOS Inverter. NMOS Gates. CMOS Inverter. CMOS Tri-State Gates. CMOS Drivers. Dynamic CMOS. BiCMOS. Latches and Flip-Flops. Semiconductor Read-Only Memories. Direct Coupled NMESFET Logic (DCFL) Inverter. Schottky Diode NMESFET Logic (SDFL) Inverter. Other Gallium Arsenide Logic Family Inverters. Gallium Arsenide NMESFET Gates. Appendices. Supplementary Reading. Selected Answers. Index.

High-Resolution Inkjet Printing of All-Polymer Transistor Circuits

Abstract: Direct printing of functional electronic materials may provide a new route to low-cost fabrication of integrated circuits. However, to be useful it must allow continuous manufacturing of all circuit components by successive solution deposition and printing steps in the same environment. We demonstrate direct inkjet printing of complete transistor circuits, including via-hole interconnections based on solution-processed polymer conductors, insulators, and self-organizing semiconductors. We show that the use of substrate surface energy patterning to direct the flow of water-based conducting polymer inkjet droplets enables high-resolution definition of practical channel lengths of 5 micrometers. High mobilities of 0.02 square centimeters per volt second and on-off current switching ratios of 10 5 were achieved.

Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations

Abstract: In this paper, we describe the design of Neurogrid, a neuromorphic system for simulating large-scale neural models in real time. Neuromorphic systems realize the function of biological neural systems by emulating their structure. Designers of such systems face three major design choices: 1) whether to emulate the four neural elements-axonal arbor, synapse, dendritic tree, and soma-with dedicated or shared electronic circuits; 2) whether to implement these electronic circuits in an analog or digital manner; and 3) whether to interconnect arrays of these silicon neurons with a mesh or a tree network. The choices we made were: 1) we emulated all neural elements except the soma with shared electronic circuits; this choice maximized the number of synaptic connections; 2) we realized all electronic circuits except those for axonal arbors in an analog manner; this choice maximized energy efficiency; and 3) we interconnected neural arrays in a tree network; this choice maximized throughput. These three choices made it possible to simulate a million neurons with billions of synaptic connections in real time-for the first time-using 16 Neurocores integrated on a board that consumes three watts.

Low-power logic styles: CMOS versus pass-transistor logic

Abstract: Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.

Energy-Optimal Mobile Cloud Computing under Stochastic Wireless Channel

Abstract: This paper provides a theoretical framework of energy-optimal mobile cloud computing under stochastic wireless channel. Our objective is to conserve energy for the mobile device, by optimally executing mobile applications in the mobile device (i.e., mobile execution) or offloading to the cloud (i.e., cloud execution). One can, in the former case sequentially reconfigure the CPU frequency; or in the latter case dynamically vary the data transmission rate to the cloud, in response to the stochastic channel condition. We formulate both scheduling problems as constrained optimization problems, and obtain closed-form solutions for optimal scheduling policies. Furthermore, for the energy-optimal execution strategy of applications with small output data (e.g., CloudAV), we derive a threshold policy, which states that the data consumption rate, defined as the ratio between the data size (L) and the delay constraint (T), is compared to a threshold which depends on both the energy consumption model and the wireless channel model. Finally, numerical results suggest that a significant amount of energy can be saved for the mobile device by optimally offloading mobile applications to the cloud in some cases. Our theoretical framework and numerical investigations will shed lights on system implementation of mobile cloud computing under stochastic wireless channel.

Analog versus digital: extrapolating from electronics to neurobiology

Abstract: We review the pros and cons of analog and digital computation. We propose that computation that is most efficient in its use of resources is neither analog computation nor digital computation but, rather, a mixture of the two forms. For maximum efficiency, the information and information-processing resources of the hybrid form must be distributed over many wires, with an optimal signal-to-noise ratio per wire. Our results suggest that it is likely that the brain computes in a hybrid fashion and that an underappreciated and important reason for the efficiency of the human brain, which consumes only 12 W, is the hybrid and distributed nature of its architecture.