Thomas E. Grebs

TL;DR: In this article, a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance.

TL;DR: In this article, various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described, and the authors also describe various methods to improve the performance.

TL;DR: In this paper, a gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode, and a gate dielectric layer is formed such that it flares out and extends directly under the body region.

TL;DR: In this article, a trench-gated field effect transistor (FET) is formed as follows: using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) one gate-runner trench has a width greater than a width of each of the active gate trench, and (ii) the plurality of open gate trenches are contiguous with the at least gate runner trenches.

TL;DR: In this article, an MOS-gated device consisting of a doped monocrystalline semiconductor substrate that includes an upper layer and is of a first conduction type is described.