Thomas E. Tkacik

Bio: Thomas E. Tkacik is an academic researcher from Motorola. The author has contributed to research in topics: On-the-fly encryption & Encryption. The author has an hindex of 7, co-authored 10 publications receiving 290 citations.

A Hardware Random Number Generator

Abstract: Some of the desirable properties a cryptographic random number generator should have are lack of bias, bit independence, unpredictiability and nonrepeatability. In this paper, we discuss how a hardware random number generator formed from simple components can provide these properties. The components include two state machines with different structures, and free-running oscillators. The generated numbers pass the DIEHARD battery of tests.

Method for purchasing items over a non-secure communication channel

Abstract: A method for purchasing items over a non-secure communication channel uses a secure communication device. The secure communication device includes a host processor, a secure memory that includes a laser-scribed encryption key, and a non-secure memory for storing encrypted data. A user's sensitive data is encrypted within the secure memory using the laser-scribed encryption key and stored as encrypted data in the non-secure memory. An encrypted credit card number and an encrypted secret key is retrieved from the non-secure memory, the encrypted credit card and secret key are decrypted with the laser-scribed encryption key, the credit card number is encrypted with a session key, and the encrypted credit card number is transferred over the network to a destination such as an internet vendor.

Method and apparatus for characterizing static and dynamic operation of an architectural system

Abstract: A method (30) and apparatus (300) for characterizing the operation of an architectural system designed through a plurality of design tasks (102-112). The design tasks are associated with architectural design rules (114-124) that compare a mapping of the system to a set of rules which are indicative of an error-free system. Objects in the mapping that do not conform to the architectural rules are identified and can be displayed at multiple architectural levels through one or more editors (26-28) and modified without leaving the editors. The system is dynamically characterized by annotating an RTL component (step 153) and simulating the system over a range of simulation cycles. The annotated component (130) monitors states of the system for storing in an analysis database (24). States at selectable simulation cycles are displayed in different orders and at multiple architectural levels.

Secure memory and processing system having laser-scribed encryption key

Abstract: A secure memory and processing system is disclosed for use in various types of communication devices. The secure processing system provides for the encryption and storage of sensitive data in a storage medium external to the secure processing system. The encrypted data is decrypted with encryption logic circuitry within the secure memory and transferred to a zeroizable memory for use by a host processor. The secure memory uses a laser-scribed encryption key coupled to encryption logic circuitry within the secure memory for encrypting and decrypting the sensitive information.

Matisse: an architectural design tool for commodity ICs

Abstract: To accelerate industrial adoption of behavioral synthesis, we have developed Matisse, an architectural design tool that increases productivity without sacrificing area, performance, or power. Matisse's main difference from traditional behavioral synthesis tools is that it lets the designer play a key role. It allows the designer to make major decisions about styles, protocols, parallelism, delays, and partial or even complete architectures before the behavioral synthesis phase starts. Then it enables the designer to incorporate these decisions into the architecture using behavioral synthesis. Matisse supports the diverse design practices required for commodity IC design by giving the designer fine-grain control of behavioral synthesis tasks.

Security Systems for Protecting an Asset

Abstract: Security systems for protecting assets are described, including password-based security systems that can provide different levels of access responsive to entry of a primary or secondary password. In some versions, user-configurable security rules can provide customized responses to entry of primary or secondary passwords, including feigned or limited access, security alerts, etc. Passwords comprising overt and covert components can be used to provide enhanced security and improved user control over system response. Improved security systems involving transactions between multiple parties are also considered, with options for user-customized security rules including primary and secondary passwords, and reverse challenge and response methods. Systems for Limited Use Credentials are also disclosed to reduce the risk of identity theft.

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Abstract: Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS msystem-on-chip design complexityethodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.

A Provably Secure True Random Number Generator with Built-In Tolerance to Active Attacks

Abstract: This paper is a contribution to the theory of true random number generators based on sampling phase jitter in oscillator rings. After discussing several misconceptions and apparently insurmountable obstacles, we propose a general model which, under mild assumptions, will generate provably random bits with some tolerance to adversarial manipulation and running in the megabit-per-second range. A key idea throughout the paper is the fill rate, which measures the fraction of the time domain in which the analog output signal is arguably random. Our study shows that an exponential increase in the number of oscillators is required to obtain a constant factor improvement in the fill rate. Yet, we overcome this problem by introducing a postprocessing step which consists of an application of an appropriate resilient function. These allow the designer to extract random samples only from a signal with only moderate fill rate and, therefore, many fewer oscillators than in other designs. Last, we develop fault-attack models and we employ the properties of resilient functions to withstand such attacks. All of our analysis is based on rigorous methods, enabling us to develop a framework in which we accurately quantify the performance and the degree of resilience of the design

Multithreaded, mixed hardware description languages logic simulation on engineering workstations

Abstract: This invention describes a multithread HDL logic simulator that is unique from the prior arts. Specifically, it can process both VHDL and Verilog languages in a single program, and it uses special concurrent algorithms to accelerate the tool's performance on multiprocessor platforms to achieve linear to super-linear scalability on multiprocessor systems. Furthermore, the invention includes a unique remote logic simulation and job scheduling capabilities.

High-Speed True Random Number Generation with Logic Gates Only

Abstract: It is shown that the amount of true randomness produced by the recently introduced Galois and Fibonacci ring oscillators can be evaluated experimentally by restarting the oscillators from the same initial conditions and by examining the time evolution of the standard deviation of the oscillating signals. The restart approach is also applied to classical ring oscillators and the results obtained demonstrate that the new oscillators can achieve orders of magnitude higher entropy rates. A theoretical explanation is also provided. The restart and continuous modes of operation and a novel sampling method almost doubling the entropy rate are proposed. Accordingly, the new oscillators appear to be by far more effective than other known solutions for random number generation with logic gates only.