Thomas Hollstein

Bio: Thomas Hollstein is an academic researcher from Tallinn University of Technology. The author has contributed to research in topics: Network on a chip & Static routing. The author has an hindex of 13, co-authored 91 publications receiving 726 citations. Previous affiliations of Thomas Hollstein include Darmstadt University of Applied Sciences & Technische Universität Darmstadt.

Multicast parallel pipeline router architecture for network-on-chip

Abstract: This paper presents a flexible mesh router architecture using synchronous parallel pipeline worm-switching supporting unicast and multicast services. A very flexible mechanism to manage broadcast-flow to share the communication link in on-chip network is proposed. The proposed machanism guarantees, that all flits in multicast packets can be accepted in their multiple destination nodes. Our Network-on-Chip (NoC) is implemented based on modular synthesizable VHDL objects. The Architecture is flexible to design new NoC prototypes. Area overhead to update the NoC from unicast to multicast with the same routing algorithm is only about 15%.

Deadlock-free routing and component placement for irregular mesh-based networks-on-chip

Abstract: Routing is one of the most crucial key factors which decides over the success of NoC architecture based systems or their failure. This paper uses well known principles from parallel computer architecture to develop a deadlock free highly adaptive routing algorithm for a 2D-mesh based network-on-chip (NoC) architecture including oversized IP cores. The paper consists of a short introduction into related routing theories and then gives a detailed description of the developed routing scheme. The last part is dedicated to a new floorplanning method, which allows to generate high density layouts suitable for the presented routing algorithm.

Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip

Abstract: This paper presents the first synthesizable network-on-chip (NoC) based on a mesh topology, which supports adaptive and deadlock-free tree-based multicast routing without virtual channels. The deadlock-free routing algorithms for unicast and multicast packets are the same. Therefore, the routing function gate-level implementation is very efficient. Multicast packets are injected to the network by sending multiple packet headers beforehand. The packet headers contain destination addresses to set up multicast trees connecting a source with multiple destination nodes. An additional locally uniform identification (ID) field is packetized together with flits belonging to the same packet. Therefore, flits of different unicast or multicast packets can be interleaved in the same queue because of the local ID-tags, which are updated and mapped dynamically to support bandwidth scalability of interconnection links. Deadlocks in tree-based multicast routing are handled using a flit-by-flit round arbitration and a fair hold-release tagging mechanism. The effectiveness of the novel mechanism has been experimented under multiple multicast conflicts scenarios, where the experimental results show that all traffic is accepted in-order and lossless in their destination nodes even if adaptive routing functions are used and the sizes of the multicast messages are very long.

Computer-aided design of fuzzy systems based on generic VHDL specifications

Abstract: In this paper, three types of fuzzy systems and related hardware architectures are discussed: standard fuzzy controllers, FuNe I fuzzy systems, and fuzzy classifiers based on a neural network structure. Two computer-aided design (CAD) packages for automatic hardware synthesis of standard fuzzy controllers are presented: a hard-wired implementation of a complete fuzzy system on a single or multiple field programmable gate arrays (FPGA) and a modular toolbox called fuzzyCAD for synthesis of reprogrammable fuzzy controllers with architectures due to specified designer constraints. In the fuzzyCAD system, an efficient design methodology has been implemented which covers a large design space in terms of signal representations and component architectures as well as system architectures. Very high speed integrated-circuits hardware-description language (VHDL) descriptions and usage of powerful synthesis tools allow different technologies to be targeted easily and efficiently. Properties and hardware realizations of fuzzy classifiers based on a neural network are introduced. Finally, future perspectives and possible enhancements of the existing toolkits are outlined.

New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networks-on-Chip

Abstract: A new theory for deadlock-free multicast routing especially used for on-chip interconnection network (NoC) is presented in this paper. The NoC router hardware solution that enables the deadlock-free multicast routing without utilizing virtual channels is introduced formally. The special characteristic of the NoC is that, wormhole packets can cut-through at flit-level and can be interleaved in the same channel with other flits of different packets by multiplexing it using a rotating flit-by-flit arbitration. The routing paths of each flit can be guaranteed correct because flits belonging to the same packet are labeled with the same local Id-tag on every communication channel. Hence, multicast deadlock problem can be solved at each router by further applying a hold-release tagging mechanism to control and manage conflicting multicast requests.

Mixed Criticality Systems - A Review

Abstract: This review covers research on the topic of mixed criticality systems that has been published since Vestal’s 2007 paper. It covers the period up to and including December 2015. The review is organised into the following topics: introduction and motivation, models, single processor analysis (including job-based, hard and soft tasks, fixed priority and EDF scheduling, shared resources and static and synchronous scheduling), multiprocessor analysis, related topics, realistic models, formal treatments, and systems issues. An appendix lists funded projects in the area of mixed criticality.

Survey of Network on Chip (NoC) Architectures & Contributions

Abstract: Multiprocessor architectures and platforms have been introduced to extend the applicability of Moore’s law. They depend on concurrency and synchronization in both software and hardware to enhance the design productivity and system performance. These platforms will also have to incorporate highly scalable, reusable, predictable, cost- and energy-efficient architectures. With the rapidly approaching billion transistors era, some of the main problems in deep sub-micron technologies which are characterized by gate lengths in the range of 60-90 nm, will arise from non-scalable wire delays, errors in signal integrity and unsynchronized communications. These problems may be overcome by the use of Network on Chip (NOC) architecture. In this paper, we have summarized over sixty research papers and contributions in NOC area.

Methods for fault tolerance in networks-on-chip

Abstract: Networks-on-Chip constitute the interconnection architecture of future, massively parallel multiprocessors that assemble hundreds to thousands of processing cores on a single chip. Their integration is enabled by ongoing miniaturization of chip manufacturing technologies following Moore's Law. It comes with the downside of the circuit elements' increased susceptibility to failure. Research on fault-tolerant Networks-on-Chip tries to mitigate partial failure and its effect on network performance and reliability by exploiting various forms of redundancy at the suitable network layers. The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years. It is structured along three communication layers: the data link, the network, and the transport layers. The most important results are summarized and open research problems and challenges are highlighted to guide future research on this topic.