Flash ADC is the fastest analog to digital converter, also known as parallel ADC. It is ideal for applications requiring large bandwidth. It consists of a resistor ladder, comparator and an encoder circuit. Output of the comparator is a thermometer code. It has to be converted to corresponding binary code using suitable encoder. Decreasing power dissipation of an encoder is a major concern while designing low power Flash ADC. This paper compares various encoder circuits such as ROM encoder, fat tree encoder, Wallace tree encoder and MUX based encoder. Even though fat tree encoder is the fastest encoder, it is more complex in structure. This makes the layout design difficult. Wallace tree encoder is best in terms of bubble error correction, but it consumes more power. Among these multiplexer based encoder is more power efficient and simple in design. So it is more suitable for low power Flash ADC design.

Thermometer code to Binary code Converter for Flash ADC - A Review

Digital Frequency Meter is deployed to figure out the frequency of digital signals, that foots its application in vibration monitoring, optical sensor readout and for testing digital logics etc. The basic behind the PSoC based Frequency Meter, is to employ Pulse Width Modulator blocks and Counters blocks along with software manipulation to evaluate frequency of the given digital signal. PSoC 3 processor CY8C3866AX has the maximum Bus Frequency of 24MHz, according to the Counter specification the maximum allowable counter frequency is 12MHz. The design implemented uses the full efficiency of both the specification mentioned above and capable of measuring frequency from 1Hz to 12MHz, with the error of 0 percentage at low frequencies up to 10KHz, error of 0.09 percentage up to 1MHz and, error of 1.3 percentage for high frequencies. Making the frequency meter On-Chip, helps in designing the circuit under test and the meter to be on same board, thus gaining advantage of avoiding external influence over testing.

PSoC embedded design for ultra low digital frequency meter

Digital watermarking always attracts the attention of researchers from early nineties to present scenario, in the ever changing world of digital creation, transmission and modification of information. In this paper we draw our attention towards a next generation of digital watermarking based on specific features of digital information using Harris corner detection (strongest) method. In this scheme first twenty strongest corner points obtained using Harris method are used as a reference for embedding watermark information and to retain the synchronization information after distortions. The scheme is time efficient as only twenty strongest corner points per frame are computed. Hence the proposed scheme is useful for time constrained applications. The experimental results confirms that the suggested scheme show a adequate level of resilience against the majority of image processing attacks together with affine transformations.

Next Generation Noise and Affine Invariant Video Watermarking Scheme Using Harris Feature Extraction

The watermarking technique can be considered as an important mechanism to protect the Intellectual Property Rights (IPR) of multimedia contents. Currently, most of multimedia contents are exchanged online in a digital form, which exposes the content to be illegal alteration easily without recognize theoffenders. Digital watermarking is used to embed a watermark into the digital media in such away that can not be discovered from the original watermarked data. Consequently, the watermark can be removed and used to verify the copyright ownership of that digital media. In this paper, a hybrid watermarking technique based on Least Significant Bit (LSB) and Discrete Wavelet Transform (DWT) is introduced and explained.. In order to investigate the effectiveness of the proposed hybrid technique in terms of robustness and imperceptibility, a comparison between the three techniques is also presented. This comparison was carried out using Peak Signal to Noise Ratio (PSNR), Mean Square Error (MSE), and Structural Similarity Index Measure (SSIM). The SSIM results were very close to 1, which means that the recovered watermarks from watermarked image were not distorted in the three cases. The PSNR and MSE values show that the quality of the watermarked images using the proposed technique is better compared to that watermarked images using standalone LSB and DWT. Moreover, the results prove that the proposed hybrid technique was more effective in terms of robustness and imperceptibility compared to LSB and DWT techniques

Digital Image Watermarking Method Based on LSB and DWT Hybrid Technique

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

Watermarking is a technology that complements cryptography by embedding imperceptible signals in work. Information hiding techniques have recently become important in a number of application areas. Digital audio, video and images are increasingly furnished with distinguishing but imperceptible marks, which may contain a hidden copyright notice that helps to prevent unauthorized copying directly. One approach is to introduce an invisible image known as digital watermark, into an image sequence. This paper presents secured algorithms for embedding digital watermarks into images. The proposed method performs imperceptible watermarking of images in frequency domain. The watermark is embedded in the DWT and DCT domain of an image in a multi-resolution way. In the decoding phase, once the watermark is extracted from the watermarked image, certain performance measures such as peak signal to mean noise ratio (PSNR) and correlation are calculated. Different types of attacks have been applied to the watermarked image to test the robustness of the applied technique and for each case, PSNR and correlation are calculated. Even though DWT method gives better results when compared to DCT, performances of both methods are good.

Digital image watermarking in frequency domain

In this project, a Flash ADC with TIQ(Threshold Inverter Quantizer) comparator and a Wallace tree encoder is described. Both DC and transient analysis report for 3 bit ADC are included. A comparison between Wallace tree and ROM encoder is included in the project illustrating how power can be reduced using Wallace tree encoder instead of ROM encoder. The design was successfully simulated for piece-wise linear and sinusoidal input. The 4 bit and 5 bit flash ADC with TIQ comparator and Wallace tree encoder is also described.

A low power flash ADC with Wallace tree encoder

Image distortion may result from a variety of factors, such as changes in electronic imaging equipment that create noise. The goal of blur image alignment is to determine which images are blurred and to restore them. Due to this, a unique blurred image restoration approach is developed, which consists of a point spread function, canny edge detection, GLCM extraction, and general regression neural network for identifying the type of blurred images, and a wiener filter for restoring the image. This technique uses a combination of the General Regression Neural Network (GRNN) and Deep Neural Network (DNN) to detect the kind of a blur and determine the calibration efficiency of the DNN and the degradation efficiency of the GRNN. The mean square error (MSE), the covariance factor, and the peak signal-to-noise ratio (PSNR) are used to assess the effectiveness of the proposed method. In comparison to conventional procedures, the proposed method yields superior outcomes.

A General Regression Neural Network based Blurred Image Restoration

The main aim of this paper is to design the digital frequency meter with frequency analyzing module. As a measuring frequency's instrument, the cymometer often refer to as electronic counter in modern electronic technology. Its basic function is to measure the signal frequency and this frequency counter has a wide range of applications. It is not only used in the general simple instrument's measurement, but also used in teaching, research, high-precision instruments measuring, industrial control and other areas. Currently, the high-performance and simple-structure electronic products have become the mainstay of market. In this project the cymometer not only measure the frequency but also determines the jitter, glitches status etc., Digital Frequency Meter were designed using VHDL language and simulated using Modelsim 6.3v simulator. In order to increase the efficiency of the system, sleep mode concept is introduced, which reduces unwanted circuit power utilization.

Design and simulation of digital frequency meter using VHDL

In this paper Low power multipliers can be designed by using new technique. This technique introduces new hybrid full adders and compressors. The new adders allow NAND gates to generate most of the multiplier partial product bits instead of AND gates and inverters which were used in signed multipliers like Baugh-wooley multipliers, thereby lowering the power consumption and the total number of required transistors. In this paper 8×8 array multipliers, baugh-wooley multipliers are designed by using this hybrid adders and tree multipliers are designed by using compressors and the power, area, delay of these multipliers are compared. For an 8×8 implementation, the ALL-NAND array multiplier achieves reduction interms of power consumption and 7.8 % reduction in transistor count with increase in time delay compared to baugh-wooley multiplier. The ALL-NAND tree multiplier exhibits lower power consumption and 7.3% reduction in transistor count, with longer time delay, compared to conventional tree multiplier. The simulation results are obtained by tsmc 0.18nm technology.

Thottempudi Pardhu

Papers

Digital image watermarking in frequency domain

A low power flash ADC with Wallace tree encoder

A General Regression Neural Network based Blurred Image Restoration

Design and simulation of digital frequency meter using VHDL

Design of ultra low power multipliers using hybrid adders