Tiago Pessoa

Bio: Tiago Pessoa is an academic researcher from Instituto Superior Técnico. The author has contributed to research in topics: Evolutionary computation & Crossover. The author has an hindex of 1, co-authored 1 publications receiving 4 citations.

Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel

Abstract: State-of-the-art design of analog and radio frequency integrated circuits is often accomplished using sizing optimization. In this paper, an innovative combination of principal component analysis (PCA) and evolutionary computation is used to increase the optimizer's efficiency. The adopted NSGA-II optimization kernel is improved by applying the genetic operators of mutation and crossover on a transformed design-space, obtained from the latest set of solutions (the parents) using PCA. By applying crossover and mutation on variables that are projections of the principal components, the optimization moves more effectively, finding solutions with better performances, in the same amount of time, than the standard NSGA-II optimization kernel. The proposed method was validated in the optimization of two widely used analog circuits, an amplifier and a voltage controlled oscillator, reaching wider solutions sets, and in some cases, solutions sets that can be almost 3 times better in terms of hypervolume.

Geometrical representations for MCDA

Abstract: In this paper geometrical representations for multicriteria decision problems are proposed. This new approach provides assistance to understand the conflictual aspects of the criteria and to tackle the problem of the weights associated to them. A generalized criterion, including a preference function, is first generated for each criterion. This allows to define unicriterion preference flows for which a geometrical representation can be obtained by using the Principal Components Analysis. The actions are represented by points and criteria by axes in the PCA plane. A decision axis taking into account the weights associated to the criteria can be defined. This technique provides the decision-maker with a considerable enrichment for the understanding of his problem: clusters of actions can be considered, the importance of the criteria can be evaluated, conflictual criteria are immediately detected, incomparability between actions is emphasized and explained, best compromise actions are easily selected, new decision-axes representing possible clusters of criteria can be considered, undesirable actions can be eliminated, … The technique consists in a powerful new qualitative decision tool. It is illustrated in the paper on some examples treated by the Promethee I and II methods. A didactic and user-friendly microcomputer code is available.

STAIC: An Interactive Framework for Synthesizing CMOS and BiCMOS Analog Circuits

Abstract: STAIC is an interactive design tool that synthesizes CMOS and BiCMOS analog integrated circuits that conform to specified performance constraints. STAIC features an input modeling language for entering hierarchical circuit descriptions and a symbolic/numeric solve unit that dynamically integrates analytical model equations across hierarchical boundaries. Output of the solver is a ??flattened?? homogeneous model that is customized to a user specified topology and set of performance specifications. The output is thus tailored for optimization and other numerically intense design exploration procedures. All model descriptions include physical layout so that important net parasitics may be fully accounted for during design evaluation. Synthesis proceeds via a successive solution refinement methodology. Multilevel models of increasing sophistication are used by scan and optimization modules to converge to what is likely a globally optimal solution. Design experiments have shown that STAIC can produce satisfactory results.

A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications

Abstract: Advancements of Machine Learning (ML) in the field of computer vision have paved the way for its potential application in many other fields. Researchers and hardware domain experts are exploring possible applications of Machine Learning in optimizing many aspects of hardware development process. In this paper, we propose a novel approach for predicting the area of hardware components from specifications. The flow uses an existing RTL generation framework, for generating valid data samples that enable ML algorithms to train the learning models. The approach has been successfully employed to predict the area of real-life hardware components such as Control and Status Register (CSR) interfaces that are ubiquitous in embedded systems. With this approach we are able to predict the area with more than 98% accuracy and 600x faster than the existing methods. In addition, we are able to rank the features according to their importance in final area estimations.

Asynchronous Parallel Expected Improvement Matrix-Based Constrained Multi-Objective Optimization for Analog Circuit Sizing

Abstract: In this brief, we propose an efficient asynchronous parallel expected improvement matrix-based (EIM) constrained multi-objective optimization approach with mixed models for analog circuit sizing. In contrast to other asynchronous methods for single-objective optimization, our method aims to solve multi-objective problems with multiple constraints. The proposed new asynchronous strategy can parallelize not only circuit simulations but also the process of building models. We introduce an EIM criterion for objectives as the acquisition function and build radial basis function models for constraints. The proposed method is based on prescreening instead of internal optimization to further reduce the computational cost of models. Experimental results on two real-world circuits illustrate that when the batch size is 15, our proposed method provides with better trade-off information and reduces the total runtime of the optimization by up to 92X compared with NSGA-II. There is a speedup of up to 8X and 4X compared with the state-of-the-art synchronous approach and asynchronous approach in terms of the runtime.