scispace - formally typeset
Search or ask a question
Author

Tim Baldauf

Other affiliations: GlobalFoundries
Bio: Tim Baldauf is an academic researcher from Dresden University of Technology. The author has contributed to research in topics: Transistor & Nanowire. The author has an hindex of 12, co-authored 30 publications receiving 415 citations. Previous affiliations of Tim Baldauf include GlobalFoundries.

Papers
More filters
Journal ArticleDOI
TL;DR: The RFET basics and current status are reviewed and the state of the art of reconfigurable devices will be summarized and the RFET will be introduced together with related devices based on silicon nanowire technology.
Abstract: With CMOS scaling reaching the limits in the next decade, new approaches are required to enhance the functionality of electronic systems. Reconfigurability on the device level promises to realize more complex systems with a lower device count. In the last 5 years a number of interesting concepts have been proposed to realize such a device level reconfiguration. Among these the reconfigurable field effect transistor (RFET), a device that can be configured between an n-channel and p-channel behavior by applying an electrical signal, can be considered as an end of roadmap extension of current technology with only small modifications to the process flow [1]. This paper gives a review on the RFET basics and current status. In the first sections the state of the art of reconfigurable devices will be summarized [2] and the RFET will be introduced together with related devices based on silicon nanowire technology [3]. The device optimization with respect to device symmetry and performance will be discussed next [4,5]. The potential of the RFET device technology will then be shown by discussiing circuit implementations making use of the unique advantages of this device concept [6,7,8]. The basic device concept was also extended towards applications in flexible devices and sensors [9,10] extending the capabilities also towards so called More than Moore applications were new functionalities are implemented in CMOS base processes. Finally the prospects of the RFET device technology will be discussed.

97 citations

Journal ArticleDOI
TL;DR: Reconfigurable silicon nanowire field-effect transistors (RFETs) combine the functionality of classical unipolar p-type and n-type FETs in one universal device, and it is shown that an asymmetric transistor layout with individual optimization of both top gates can be used to increase the speed of those circuits.
Abstract: Reconfigurable silicon nanowire field-effect transistors (RFETs) combine the functionality of classical unipolar p-type and n-type FETs in one universal device. In this paper, we show devices exhibiting full symmetry between p- and n-functionality, while having identical geometry. Scaling trends and feasibility for digital circuit integration are evaluated based on TCAD simulations. The method of logical effort is applied to analyze fundamental differences in circuit topology using this unique type of multigate transistors. We introduce a set of multifunctional logic gates based on RFETs providing all basic Boolean functions, including nand / nor , and / or, and xor/xnor, and compared them with classical implementations. Two 1-bit full adders based on those gates are presented as an insightful example that RFETs are one possible solution to increase the system functionality. Moreover, it is shown that an asymmetric transistor layout with individual optimization of both top gates can be used to increase the speed of those circuits.

96 citations

Journal ArticleDOI
17 Jan 2017-ACS Nano
TL;DR: Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.
Abstract: Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element...

73 citations

Journal ArticleDOI
TL;DR: In this paper, a top-down single-gated Schottky barrier transistor is presented exhibiting the highest symmetry of on-currents for n- and p-conductance of such silicon-on-insulator-based devices.
Abstract: In this paper, a technology for top-down single-gated Schottky barrier transistor is presented exhibiting the highest symmetry of on-currents for n- and p-conductance of such silicon-on-insulator-based devices. The symmetry in the current-voltage-characteristics is a mandatory requirement to realize circuits with reconfigurable nanowire field effect transistors (RFETs) whose channel can be switched electrostatically between n- and p-conductance. It was achieved by an oxidation-induced stressor layer covering the nanowire. Together with the demand for only a single gate potential level, this opens the route to build top-down RFET circuits. Our device features an atomically sharp Schottky junction between intruded nickel silicide and the intrinsic nanowire channel.

36 citations

Proceedings ArticleDOI
14 Mar 2016
TL;DR: It is found that especially complex functions, like Majority and Parity gates of many inputs, which are generally avoided in standard CMOS technology, benefit from the new device type.
Abstract: We present MUX based programmable logic circuits built from newly proposed compact and efficient designs of combinational logic gate. These are enabled by reconfigurable Schottky barrier nanowire transistors with multiple independent gates, which can be dynamically switched between p- and n-type functionality. It will be shown that a single device can be used to replace paths of several transistors in series. This leads to topological differences and increased flexibility in circuit design. We found that especially complex functions, like Majority and Parity gates of many inputs, which are generally avoided in standard CMOS technology, benefit from the new device type. This can be exploited to directly map reconfigurable building blocks, e.g. dynamically switching NAND to NOR. Exemplary 6-functional logic circuits will be shown, which exhibit up to 80% reduction in transistor count, while maintaining the same functionality as compared to the CMOS reference design. Logical effort analysis indicates that 20% less circuit delay and 33% less normalized dynamic power consumption can be achieved.

34 citations


Cited by
More filters
Patent
10 Feb 2014
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

259 citations

Journal ArticleDOI
TL;DR: A comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics, including a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics.
Abstract: Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

189 citations

01 Jan 2016
TL;DR: The logical effort designing fast cmos circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you for reading logical effort designing fast cmos circuits. As you may know, people have search numerous times for their chosen novels like this logical effort designing fast cmos circuits, but end up in infectious downloads. Rather than reading a good book with a cup of coffee in the afternoon, instead they are facing with some harmful bugs inside their desktop computer. logical effort designing fast cmos circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our book servers hosts in multiple locations, allowing you to get the most less latency time to download any of our books like this one. Merely said, the logical effort designing fast cmos circuits is universally compatible with any devices to read.

137 citations

Journal ArticleDOI
29 Jun 2018-ACS Nano
TL;DR: This work shows a path to enable doping-free low-power electronics on 2D semiconductors, going beyond the concept of unipolar physically doped devices, while suggesting a road to achieve higher computational densities in two-dimensional electronics.
Abstract: Atomically thin two-dimensional (2D) materials belonging to transition metal dichalcogenides, due to their physical and electrical properties, are an exceptional vector for the exploration of next-generation semiconductor devices. Among them, due to the possibility of ambipolar conduction, tungsten diselenide (WSe2) provides a platform for the efficient implementation of polarity-controllable transistors. These transistors use an additional gate, named polarity gate, that, due to the electrostatic doping of the Schottky junctions, provides a device-level dynamic control of their polarity, that is, n- or p-type. Here, we experimentally demonstrate a complete doping-free standard cell library realized on WSe2 without the use of either chemical or physical doping. We show a functionally complete family of complementary logic gates (INV, NAND, NOR, 2-input XOR, 3-input XOR, and MAJ) and, due to the reconfigurable capabilities of the single devices, achieve the realization of highly expressive logic gates, suc...

98 citations

Journal ArticleDOI
TL;DR: The RFET basics and current status are reviewed and the state of the art of reconfigurable devices will be summarized and the RFET will be introduced together with related devices based on silicon nanowire technology.
Abstract: With CMOS scaling reaching the limits in the next decade, new approaches are required to enhance the functionality of electronic systems. Reconfigurability on the device level promises to realize more complex systems with a lower device count. In the last 5 years a number of interesting concepts have been proposed to realize such a device level reconfiguration. Among these the reconfigurable field effect transistor (RFET), a device that can be configured between an n-channel and p-channel behavior by applying an electrical signal, can be considered as an end of roadmap extension of current technology with only small modifications to the process flow [1]. This paper gives a review on the RFET basics and current status. In the first sections the state of the art of reconfigurable devices will be summarized [2] and the RFET will be introduced together with related devices based on silicon nanowire technology [3]. The device optimization with respect to device symmetry and performance will be discussed next [4,5]. The potential of the RFET device technology will then be shown by discussiing circuit implementations making use of the unique advantages of this device concept [6,7,8]. The basic device concept was also extended towards applications in flexible devices and sensors [9,10] extending the capabilities also towards so called More than Moore applications were new functionalities are implemented in CMOS base processes. Finally the prospects of the RFET device technology will be discussed.

97 citations