Showing papers by "Timo Hämäläinen published in 2008"

Ultra-Low Energy Wireless Sensor Networks in Practice: Theory, Realization and Deployment

Abstract: Finally a book on Wireless Sensor Networks that covers real world applications and contains practical advice! Kuorilehto et al. have written the first practical guide to wireless sensor networks. The authors draw on their experience in the development and field-testing of autonomous wireless sensor networks (WSNs) to offer a comprehensive reference on fundamentals, practical matters, limitations and solutions of this fast moving research area. Ultra Low Energy Wireless Sensor Networks in Practice: Explains the essential problems and issues in real wireless sensor networks, and analyzes the most promising solutions. Provides a comprehensive guide to applications, functionality, protocols, and algorithms for WSNs. Offers practical experiences from new applications and their field-testing, including several deployed networks. Includes simulations and physical measurements for energy consumption, bit rate, latency, memory, and lifetime. Covers embedded resource-limited operating systems, middleware and application software. Ultra Low Energy Wireless Sensor Networks in Practice will prove essential reading for Research Scientists, advanced students in Networking, Electrical Engineering and Computer Science as well as Product Managers and Design Engineers.

A Wireless Sensor Network for RF-Based Indoor Localization

Abstract: An RF-based indoor localization design targeted for wireless sensor networks (WSNs) is presented. The energy-efficiency of mobile location nodes is maximized by a localization medium access control (LocMAC) protocol. For location estimation, a location resolver algorithm is introduced. It enables localization with very scarce energy and processing resources, and the utilization of simple and low-cost radio transceiver HardWare (HW) without received signal strength indicator (RSSI) support. For achieving high energy-efficiency and minimizing resource usage, LocMAC is tightly cross-layer designed with the location resolver algorithm. The presented solution is fully calibration-free and can cope with coarse grained and unreliable ranging measurements. We analyze LocMAC power consumption and show that it outperforms current state-of-the-art WSN medium access control (MAC) protocols in location node energy-efficiency. The feasibility of the proposed localization scheme is validated by experimental measurements using real resource constrained WSN node prototypes. The prototype network reaches accuracies ranging from 1 m to 7 m.With one anchor node per a typical office room, the current room of the localized node is determined with 89.7% precision.

Rapid design and evaluation framework for wireless sensor networks

Abstract: The diversity of applications and typically scarce node resources set very tight constraints to Wireless Sensor Networks (WSN). It is not possible to fulfill all requirements with a general purpose WSN, for which reason the rapid development of application specific WSNs is preferred. We present a new framework called WIreless SEnsor NEtwork Simulator (WISENES) for the design, simulation, and evaluation of WSNs. The target WSN is designed in Specification and Description Language (SDL), simulated in WISENES, and implemented on target platform either through automatic code generation or manually. The high-level WSN model is back-annotated with the measured values from a real platform. In this way, very accurate WSN simulations can be performed with a rapid design cycle. WISENES itself has been verified with TUTWSN (Tampere University of Technology Wireless Sensor Network) and ZigBee protocols. The MAC protocol of ZigBee was designed in two weeks from scratch by one designer, which shows the effectiveness of WISENES. For accuracy comparison, the results show 6.7% difference between the modeled and measured TUTWSN prototype power consumption. WISENES hastens the evaluation of new protocol and application configurations, especially for the large scale and long-term WSN deployments.

A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms

Abstract: This paper proposes an efficient parallel memory system for algorithms applied in fixed and variable block-size motion estimation (VBSME). The proposed system is implemented by a novel combination of two parallel memory architectures. The distribution of data among the memory modules is modified over contemporary approaches and the optimized address computation unit enables a rapid address generation for accessed memory locations. Furthermore, the introduced data permutation scheme organizes data efficiently for storage and retrieval. The proposed system enables up to 4 X speedup in data storage and retrieves data up to 55% faster for VBSME compared with the reference implementations. With a 0.18- mum CMOS technology, the proposed memory addressing and data permutation scheme can be clocked at 980 MHz operating frequency with a cost of less than 6 kgates. On FPGA, the system can operate at 200 MHz with less than 700 logic elements. The results show that the proposed system is applicable to real-time VBSME at HDTV resolution.

ARQ Aware Scheduling for the IEEE 802.16 Base Station

Abstract: The IEEE 802.16 technology defines the ARQ mechanism that enables a connection to resend data at the MAC level if an error is detected. In this paper, we analyze the ARQ aware scheduling for the 802.16 base station. In particular, we consider how the BS scheduler can account for the ARQ block size, absence of the ARQ block rearrangement, and the ARQ transmission window. We propose a set of constraints that can be applied to any base station scheduler algorithm. To test them, we run a number of simulation scenarios. The simulations results confirm that the ARQ aware scheduling can improve the overall performance.

Best Practices for Simulated Annealing in Multiprocessor Task Distribution Problems

Abstract: Simulated Annealing (SA) is a widely used meta-algorithm for complex optimization problems. This chapter presents methods to distribute executable tasks onto a set of processors. This process is called task mapping. The most common goal is to decrease execution time via parallel computation. However, the presented mapping methods are not limited to optimizing application execution time because the cost function is arbitrary. The cost function is also called an objective function in many works. A smaller cost function value means a better solution. It may consider multiple metrics, such as execution time, communication time, memory, energy consumption and silicon area constraints. Especially in embedded systems, these other metrics are often as important as execution time. A multiprocessor system requires exploration to find an optimized architecture as well as the proper task distribution for the application. Resulting very large design space must be pruned systematically with fast algorithms, since the exploration of the whole design space is not feasible. Iterative algorithms evaluate a number of application mappings for each architecture, and the best architecture and mapping is selected in the process. The optimization process is shown in Figure 1(a). The application, the HW platform and an initial solution are fed to a mapping component. The mapping component generates a new solution that is passed to a simulation component. The simulation component determines relevant metrics of the solution. The metrics are passed to a cost function which will evaluate the badness (cost) of the solution. The cost value is passed back to the mapping component. The mapping component will finally terminate the optimization process and output a final solution. The system that is optimized is shown in Figure 1(b). The system consists of the application and the HW platform. The application consists of tasks which are mapped to processing elements (PEs). The PEs are interconnected with a communication network. The chapter has two focuses: • optimize the cost function and • minimize the time needed for simulated annealing. First, the task distribution problem is an NP problem which implies that a heuristic algorithm is needed. The focus is on reaching as good as possible mapping. Unfortunately the true optimum value is unknown for most applications, and therefore the relative O pe n A cc es s D at ab as e w w w .ite ch on lin e. co m

On ARQ feedback intensity of the IEEE 802.16 ARQ mechanism

Abstract: The IEEE 802.16 standard defines the ARQ mechanism as a part of the MAC layer. The functioning of the ARQ mechanism depends on a number of parameters. The IEEE 802.16 specification defines them but it does not provide concrete values and solutions. We ran simulation scenarios to study how the ARQ feedback intensity impacts the performance of application protocols. The simulation results reveal that a low ARQ feedback intensity results only in a marginal improvement. Though it is possible to optimize the ARQ feedback intensity, it is reasonable to rely upon more frequent ARQ feedback messages as they do not result in a performance degradation. At the same time, ARQ connections, which work on top of HARQ, can delay the ARQ feedbacks up to the ARQ retry timeout to optimize the performance.

Distributed bus arbitration algorithm comparison on FPGA-based MPEG-4 multiprocessor system on chip

Abstract: The communication is predicted to pass the computation as the limiting factor of performance of complex digital circuits. The shared bus is the most common communication medium in system on chip (SoC) and buses have significantly evolved along increased requirements. One of the new properties of the buses is distributed arbitration. The study presents a novel dynamically adaptive arbitration algorithm and compares it with round-robin, priority, their combination and random algorithms, all with varying parameters. Algorithms are compared in two multiprocessor SoCs with 4 and 11 processors with IP blocks on field programmable gate array (FPGA). The algorithms are benchmarked with a complete MPEG-4 encoder. Different bus utilisation levels are considered by scaling the bus frequency with respect to speed of the processors. Results show that the arbitration algorithm may account for up to 1.6 times increase in performance and optimising the transfer lengths may yield speed-up of 4.4 times in application execution. The proposed dynamically adaptive arbitration was found to be the best overall algorithm in performance.

Embedded Software Architecture for Diagnosing Network and Node Failures in Wireless Sensor Networks

Abstract: Wireless Sensor Networks (WSNs) consist of embedded and distributed sensor nodes that operate on harsh operating conditions and with limited energy resources. To ensure the desired level of service, it is essential to detect and correct occurring network and node problems. In this paper, we propose a diagnostics software architecture for WSNs consisting of self-diagnostics on embedded sensor nodes and management tools for network analysis. We define a minimum set of diagnostics information that needs to be collected for analyzing the network errors and performance. To minimize communication overhead, collected information is categorized and only needed categories are requested from nodes. The diagnostics architecture is verified with a practical WSN implementation.

Configurable data memory for multimedia processing

Abstract: In modern multimedia applications, memory bottleneck can be alleviated with special stride data accesses. Data elements in stride access can be retrieved in parallel with parallel memories, in which the idea is to increase memory bandwidth with several memory modules working in parallel and feed the processor with only necessary data. Arbitrary stride access capability with interleaved memories is described in previous research where the skewing scheme is changed at run time according to the currently used stride. This paper presents the improved schemes which are adapted to parallel memories. The proposed novel parallel memory implementation allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories. Moreover, the possible access locations are unrestricted and the accessed data element count equals to the number of memory modules. Timing and area estimates are given for Altera Stratix FPGA and 0.18 micrometer CMOS process with memory module count from 2 to 32. The FPGA results show 129 MHz clock frequency for a system with 16 memory modules when read and write latencies are 3 and 2 clock cycles, respectively. The complexity of the proposed system is shown to be a trade-off between application specific and highly configurable parallel memory system.

On the credibility of load-latency measurement of network-on-chips

Abstract: This paper studies the impact of various simulation and network-on-chip (NoC) setups in common load-latency curves that are used for performance evaluation. The different setups yield very large variation in the observed performance yet they are too often undocumented. Vague definitions make the comparison of NoCs hard or impossible since the large uncertainties hide the actual differences between compared networks. Hence, this paper presents guidelines for performing load-latency measurements for network-on-chips to avoid these pitfalls.

Real-time execution monitoring on multi-processor system-on-chip

Abstract: In system-level design, design space exploration (DSE) produces large amounts of data when exploring myriad of alternatives for application mapping and the underlying platform. Visualization of the essential execution data makes the right design decisions essentially easier. This paper presents execution monitor, a versatile monitoring tool implemented in Java, for multi-processor systems-on-chip (MPSoCs). It allows monitoring both the application and the underlying platform in real-time, and also viewing the previously recorded execution trace. Execution monitor can be used both during the simulation and prototyping. Moreover, the designer can rapidly evaluate in run-time the performance of multiple application mappings via intuitive drag-and-drop mechanism. The case study shows that the visualization of the monitored execution data significantly eases optimizing the performance of the video codec after addition of new application functionality.

Evaluation of heterogeneous multiprocessor architectures by energy and performance optimization

Abstract: Design space exploration aims to find an energy-efficient architecture with high performance. A trade-off is needed between these goals, and the optimization effort should also be minimized. In this paper, we evaluate heterogeneous multiprocessor architectures by optimizing both energy and performance for applications. Ten random task graphs are optimized for each architecture, and evaluated with simulations. The energy versus performance trade-off is analyzed by looking at Pareto optimal solutions. It is assumed that there is a variety of processing elements whose number, frequency and microarchitecture can be modified for exploration purposes. It is found that both energy-efficient and well performing solutions exist, and in general, performance is traded for energy-efficiency. Results indicate that automated exploration tools are needed when the complexity of the mapping problem grows, starting already with our experiment setup: 6 types of PEs to select from, and the system consists of 2 to 5 PEs. Our results indicate that our Simulated Annealing method can be used for energy optimization with heterogeneous architectures, in addition to performance optimization with homogeneous architectures.

Application Server for Wireless Sensor Networks

Abstract: Wireless Sensor Networks (WSN) can be used in various applications for home and industrial environments The main challenges in these applications come from the requirement of collecting and presenting continuously changing sensor data Powerful abstractions are required in order to support diverse WSN configurations and the varying user requirements for sensor data visualization In this paper, we present the design of an application server for WSNs and the implementation of a server prototype referred to as TUTWSN Application Server (TAS) TAS offers services for permission management, information storing, visualization of sensor data, and messaging required for receiving sensor data from the WSNs in real-time

Bandwidth allocation and pricing in multinode network

Abstract: This paper presents adaptive resource sharing model that uses a revenue criterion to allocate network resources in the optimal way. The model ensures QoS requirements of data flows and, at the same time, maximizes the total revenue by adjusting parameters of the underlying scheduler. Besides, the adaptive model eliminates the need to find the optimal static weight values because they are calculated dynamically. The simulation consists of several cases that analyse the model and the way it provides the required QoS guarantees. The simulation reveals that the installation of the adaptive model increases the total revenue and ensures the QoS requirements for all service classes.

XML Based 3G/LTE Network and Service Management Concept

Abstract: This paper describes a new way of implementing converged wireless network and service management system using XML as the management message language and SOAP/HTTP as the protocols for configuration, performance, fault and alarm communication between network operation and maitenance (O&M) system and network elements (NE) and service provider's service production systems. Principles described in this article are fully tested and applicable and can be exploited in any current network and service management system.

Flexible management of shared resources on multiprocessor system on chip

Abstract: This paper presents a new method for run-time management of shared processing resources in multiprocessor systems on chip. A centralized resource manager unit performs dynamic allocation of shared processing resources according to the system state and given constraints. It implements a hardware mutual exclusion so that no inter-processor synchronization is required for accessing the resources. Moreover, it supports dynamic power management. In addition, a hardware implementation of the resource manager is proposed. In a case study, a resource manager is evaluated in a data-parallel MPEG-4 video encoder on multiprocessor system on chip on FPGA. The RM eases the design of six different architectures featuring two to twelve shared hardware accelerators. Only a few accelerators are required for the best performance as the accesses are efficiently scheduled.

QoS issues in adaptive scheduling in heterogeneous networks with linear pricing scenario

Abstract: This paper presents an adaptive scheduling and CAC model for the revenue maximization. The algorithm shares limited resources to different traffic flows in a fair way, and at the same time it maximizes the revenue of the service provider. Used algorithm is derived from the linear type of revenue target function, and closed form globally optimal formula is presented. The method is computationally inexpensive, while still producing maximal revenue. Due to the simplicity of the algorithm, it can operate in the highly nonstationary environments. In addition, it is nonparametric and deterministic in the sense that it uses only the information about the number of users and their traffic flows, not about call density functions or duration distributions. One possible implementation target to the algorithm could be justify it to work with IEEE 802.11e.

Gradient scheduling algorithm for fair delay guarantee in logarithmic pricing scenario

Abstract: In this paper we propose a packet scheduling scheme for ensuring delay as a Quality of Service (QoS) requirement. For customers, fair service is given while optimizing revenue of the network service provider. Gradient type algorithm for updating the weights of a packet scheduler is derived from a revenue-based optimization problem in the logarithmic pricing scenario. Algorithm is simple to implement. We compared algorithm with optimal brute-force method. The weight updating procedure is independent on the assumption of the connection's statistical behavior, and therefore it is robust against erroneous estimates of statistics.

Portable process control with DynaControl

Abstract: Remote controlling of industrial systems requires a special approach. There are requirements for both the connection and the access terminals. The connection should provide users with reliability, security and quality, and the access terminals should be able to perform the required task. One important and at the same time a problematic requirement for a mobile controlling system is bidirectional access. In this paper we describe a system which enables bidirectional data access within 3G cellular network using a commercial service, and a prototype application for quality and usability for task performance using a terminal recognition methods.