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Timothy J. Maloney

Bio: Timothy J. Maloney is an academic researcher from Intel. The author has contributed to research in topics: Electrostatic discharge & Leakage (electronics). The author has an hindex of 19, co-authored 76 publications receiving 1338 citations.


Papers
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Journal ArticleDOI
Timothy J. Maloney1, S. Dabral
TL;DR: In this paper, the p-n-p transistor chains are made from floating n-wells in complementary metal-oxide semiconductor (CMOS) and used for power supply electrostatic discharge (ESD) clamps.
Abstract: Biased and terminated p-n-p transistor chains are made from floating n-wells in p-substrate complementary metal-oxide semiconductor (CMOS) and used for power supply electrostatic discharge (ESD) clamps. The p-n-p gain may allow a compact termination circuit to be used, resulting in a stand-alone clamp. Bipolar p-n-p action accounts for unwanted low-voltage conduction as well as for very desirable clamping of power supply overvoltages. Bias networks are used to prevent excessive leakage at high temperature. These devices are becoming crucial to success in ESD product testing of CMOS integrated circuits.

151 citations

Proceedings ArticleDOI
Timothy J. Maloney1, S. Dabral1
01 Jan 1995
TL;DR: In this article, the p-n-p transistor chains are made from floating n-wells in p-substrate CMOS and used for power supply ESD clamps.
Abstract: Biased and terminated p-n-p transistor chains are made from floating n-wells in p-substrate CMOS and used for power supply ESD clamps. The p-n-p gain may allow a compact termination circuit to be used, resulting in a stand-alone clamp. Bipolar p-n-p action accounts for unwanted low-voltage conduction as well as for very desirable clamping of power supply overvoltages. Bias networks are used to prevent excessive leakage at high temperature. These devices are becoming crucial to success in ESD product testing of CMOS integrated circuits.

96 citations

Proceedings ArticleDOI
01 Mar 1985
TL;DR: In this paper, the location of energy dissipation during an EOS/ESD event is determined by a pulsed near infrared technique, and rules for predicting location of ESD dissipation are defined.
Abstract: Using new techniques it is possible to construct an EOS/ESD equivalent circuit of a product. Location of energy dissipation during an EOS/ESD event is determined by a pulsed near infrared technique. Rules for predicting location of ESD dissipation are defined. N+-P-N+ structures and n-channel transistors suffer from a current lock-on effect, which is apparently caused by a runaway oxide trapping mechanism. Different failure mechanisms are observed at narrow and wide pulse widths. Hot electron induced damage occurs under mechanical handling conditions. On CMOS outputs the n-channel device absorbs most of the ESD, and is very fragile.

90 citations

Proceedings Article
01 Oct 2002
TL;DR: Two ESD clamp circuit design techniques have been developed to reduce cell size and to combat the effects of gate leakage that have become significant in recent generations of digital CMOS process technology.
Abstract: Two ESD clamp circuit design techniques have been developed to reduce cell size and to combat the effects of gate leakage that have become significant in recent generations of digital CMOS process technology. Such clamps have proven to be able to withstand HBM stresses of 6kV and CDM pulses of 1.2kV.

67 citations

Journal ArticleDOI
TL;DR: In this article, the authors examine how these diodes couple transient noise from the peripheral power supplies to the core power supplies during circuit operation, and how such considerations influence diode clamp design.

59 citations


Cited by
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Book
01 Jan 1995
TL;DR: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESC in Integrated Circuits Effects of Processing and Packaging.
Abstract: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

554 citations

Journal ArticleDOI
TL;DR: In this paper, a whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole chip ESDprotection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits.
Abstract: A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.

323 citations

Patent
27 Aug 2007
TL;DR: In this paper, a method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the wafer was proposed, where electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

286 citations

Patent
22 Jan 2002
TL;DR: In this paper, an integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate.
Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

255 citations