Bio: Tingyuan Nie is an academic researcher from Kōchi University. The author has contributed to research in topics: Digital watermarking & Encryption. The author has an hindex of 4, co-authored 5 publications receiving 32 citations.
••13 Jun 2005
TL;DR: A new watermarking system for IP protection on post-layout design phase where the copyright is encrypted by DES and then embedded by using an incremental router into the layout design with almost 100% success for embedding.
Abstract: In this paper, we introduce a new watermarking system for IP protection on post-layout design phase. Firstly the copyright is encrypted by DES (data encryption standard) and then embedded by using an incremental router into the layout design. This watermarking technique uniquely identifies the circuit origin, yet is difficult to be detected or fabricated. The incremental router consists of a rip-up and a special re-router that inserts redundant bends into wires probabilistic. We evaluated the technique on various generated benchmark circuits to validate the completeness of the procedure. The results show it achieves almost 100% success for embedding with no extra area cost on design performances.
••19 May 2013
TL;DR: The experimental results show that the method has low resource and timing overhead, while proves a strong certificate both of IP owner and users.
Abstract: With the increasing risk of IP reuse in System on Chip (SoC) design, intellectual property (IP) techniques becomes one of the most important issues. Compare with watermarking, fingerprinting is a more effective method because is not only protects the IP owner's benefits but also user's rights. In this paper, we firstly propose a multilevel fingerprinting method for IP protection. In the typical field programmable gate array (FPGA) design flow, we first embed the watermarks into a FPGA design at netlist level by manipulating LUTs. When the IP core is compiled into a bitstream file, an individual fingerprint from IP user is then embedded into margin of FPGA. The experimental results show that the method has low resource and timing overhead, while proves a strong certificate both of IP owner and users.
TL;DR: A new efficient watermarking system for IPP on post-layout design stage that uniquely identifies the circuit origin, yet is difficult to be detected or fabricated without the tool.
Abstract: IP (Intellectual Property) reuse plays an important role in modern IC design so that IP Protection (IPP) technique is get concerned. In this paper, we introduce a new efficient watermarking system for IPP on post-layout design stage. The signature (which indicates the designer) is encrypted with a secret key by DES (Data Encryption Standard) to produce a bit string, which is then embedded into the layout design as constraints by using a specific incremental router. Once the design is watermarked successfully, the signature can be extracted accurately by the system. The system also has a strong resistance to the attack on watermarking due to the DES functionality. This watermarking technique uniquely identifies the circuit origin, yet is difficult to be detected or fabricated without our tool. We evaluated the watermarking system on IBM-PLACE 2.0 benchmark suites. The results show the system robustness and strength: the system success probability achieves 100% in suitable time with no extra area and wire length cost on design performances.
••23 May 2005
TL;DR: A new watermarking system for VLSI layout design intellectual property protection (IPP) that will not damage circuit properties by using a special incremental router that removes wires of target nets and re-routes them by inserting redundant bends.
Abstract: We propose a new watermarking system for VLSI layout design intellectual property protection (IPP) that will not damage circuit properties. The previous studies for layout design IPP are mainly restricted to pre-layout design, i.e. they would increase layout size and vary signal timing. The idea of our system is to use a special incremental router that removes wires of target nets and re-routes them by inserting redundant bends. We can distinguish the marked net from others. This redundant insertion is not always possible according to wire density around the wire, thus we use it iteratively. We evaluated the success possibilities of our watermarking system in various wire density benchmark circuits experimentally and found more than three iterations are enough for the practical post layout design to achieve successful watermarking.
••23 Apr 2010
TL;DR: This work analyzes several representative watermarking techniques from a few aspects and firstly evaluates their power by using proposed functions and hopes this work can help designers to develop stronger water marking techniques.
Abstract: With the increasing complexity of integrated circuits, system-on-chip (SoC) design is proved an effective design method due to intellectual property (IP) reuse. To protect IPs from piracy, watermarking techniques have significantly advanced as an IP protection (IPP) technique. It is an important work to judge the watermarking solutions achieve the goals or not. In this paper, we analyze several representative watermarking techniques from a few aspects and firstly evaluate their power by using proposed functions. We hope this work can help designers to develop stronger watermarking techniques.
TL;DR: A novel fingerprint template protection scheme based on chaotic encryption by using the logistic map and Murillo-Escobar's algorithm and a novel implementation in a 32 bit microcontroller for secure authentication systems to show its application on embedded expert systems.
Abstract: Chaos and fingerprint data are combined for a highly secure authentication system.Embedded system in a 32-bit microcontroller with high performance at low cost.Murillo-Escobar's algorithm is implemented to protect template and avoid identity theft.Security analysis of encryption verifies the secrecy of the personal data.Performance and resources analysis justify the implementation of the system. Fingerprint recognition is a reliable solution in user authentication systems. Nevertheless, the security and secrecy of the users data are a concern in today's biometric systems and most of the security attention is focused in biometric template protection to avoid identity theft. In recent years, several approaches have been presented where the main objective is to have the biometric revocable, but almost all them have failed in verify their security and robustness. In last years, chaotic systems have been proposed in cryptography due they have several properties related with cryptography properties such as extreme sensibility on initial conditions with confusion and ergodicity with diffusion. In this paper, we present a novel fingerprint template protection scheme based on chaotic encryption by using the logistic map and Murillo-Escobar's algorithm (Murillo-Escobar et al., 2014). In addition, we present a novel implementation of our scheme in a 32 bit microcontroller for secure authentication systems to show its application on embedded expert systems. In contrast with recent approaches presented in literature, we present a complete security analysis in both statistical and implementation level, to justify the proposed scheme in a real application. Based in the results, the proposed embedded authentication system is secure, effective and at low cost, and it could be implemented on real secure access control systems.
01 Jun 2012
TL;DR: This work proposes a novel watermarking technique to watermark FPGA bitfile for addressing weaknesses and shows that the proposed technique incurs zero overhead and is robust against removing attacks.
Abstract: Intellectual property protection (IPP) of hardware designs is the most important requirement for many Field Programmable Gate Array (FPGA) intellectual property (IP) vendors. Digital watermarking has become an innovative technology for IPP in recent years. Existing watermarking techniques have successfully embedded watermark into IP cores. However, many of these techniques share two specific weaknesses: 1) They have extra overhead, and are likely to degrade performance of design; 2) vulnerability to removing attacks. We propose a novel watermarking technique to watermark FPGA bitfile for addressing these weaknesses. Experimental results and analysis show that the proposed technique incurs zero overhead and it is robust against removing attacks.
TL;DR: The IP-based SoC design flow is discussed to highlight the exact locations and the nature of infringements in the flow, identifies the adversaries, categorizes these infringements, and applies strategic analysis on the effectiveness of the existing IPP techniques for these categories of infringement.
Abstract: Increased design complexity, shrinking design cycle, and low cost--this three-dimensional demandmandates advent of system-onchip (SoC) methodology in semiconductor industry. The key concept of SoC is reuse of the intellectual property (IP) cores. Reuse of IPs on SoC increases the risk of misappropriation of IPs due to introduction of several new attacks and involvement of various parties as adversaries. Existing literature has huge number of proposals for IP protection (IPP) techniques to be incorporated in the IP design flow as well as in the SoC design methodology. However, these are quite scattered, limited in possibilities in multithreat environment, and sometimes mutually conflicting. Existing works need critical survey, proper categorization, and summarization to focus on the inherent tradeoff, existing security holes, and new research directions. This paper discusses the IP-based SoC design flow to highlight the exact locations and the nature of infringements in the flow, identifies the adversaries, categorizes these infringements, and applies strategic analysis on the effectiveness of the existing IPP techniques for these categories of infringements. It also clearly highlights recent challenges and new opportunities in this emerging field of research.
••01 Jan 2009
TL;DR: This research focuses on providing a solution to the metering problem by restricting an attacker’s access to the IC design by modifying the CAD tool flow in order to identify locations in the circuit which can be protected with reconfigurable logic barriers.
Abstract: With each new feature size, integrated circuit (IC) manufacturing costs increase. Rising expenses cause the once vertical IC supply chain to flatten out. Companies are increasing their reliance on contractors, often foreign, to supplement their supply chain deficiencies as they no longer can provide all of the services themselves. This shift has brought with it several security concerns classified under three categories: (1) Metering controlling the number of ICs created and for whom. (2) Theft controlling the dissemination of intellectual property (IP). (3) Trust controlling the confidence in the IC post-fabrication. Our research focuses on providing a solution to the metering problem by restricting an attacker’s access to the IC design. Our solution modifies the CAD tool flow in order to identify locations in the circuit which can be protected with reconfigurable logic barriers. These barriers require the correct key to be present for information to flow through. Incorrect key values render the IC useless as the flow of information is blocked. Our selection heuristics utilize observability and controllability don’t care sets along with a node’s location in the network to maximize an attacker’s burden while keeping in mind the associated overhead. We implement our approach in an open-source logic synthesis tool, compare it against previous solutions and evaluate its effectiveness against a knowledgeable attacker.
01 Apr 2011