Toktam Taghavi

Bio: Toktam Taghavi is an academic researcher from University of Amsterdam. The author has contributed to research in topics: Design space exploration & Visualization. The author has an hindex of 5, co-authored 8 publications receiving 60 citations.

Visualization of Multi-objective Design Space Exploration for Embedded Systems

Abstract: Modern embedded systems come with contradictory design constraints. On one hand, these systems often target mass production and battery-based devices, and therefore should be cheap and power efficient. On the other hand, they need to achieve high (real-time) performance. This wide spectrum of design requirements leads to complex heterogeneous system-on-chip (SoC) architectures. The complexity of embedded systems forces designers to model and simulate systems and their components to explore the wide range of design choices. Such design space exploration is especially needed during the early design stages, where the design space is at its largest. Due to the exponential design space in real problems and multiple criteria to be considered, multi-objective evolutionary algorithms (MOEAs) are often used to trim down a large design space into a finite set of points and provide the designer a set of tradable solutions with respect to the design criteria. Interpreting the search results (e.g., where are the Pareto points located), understanding their relations and analyzing how the design space was searched by such searching algorithms is of invaluable importance to the designer. To this end, this paper presents a novel interactive visualization tool, based on tree visualization, to understand the search dynamics of a MOEA and to visualize where the optimum design points are located in the design space and what objective values they have.

Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration

Abstract: System-level computer architecture simulations create large volumes of simulation data to explore alternative architectural solutions. Interpreting and drawing conclusions from this amount of simulation results can be extremely cumbersome. In other domains that also struggle with interpreting large volumes of data, such as scientific computing, data visualization is an invaluable tool. Such visualization is often domain specific and has not become widely studied and utilized for evaluating the results of computer architecture simulations. In this paper, we describe an interactive visual tool for exploring and analyzing alternative architectural solutions at multiple levels of abstraction. As a proof of concept, we have used this tool to create a coordinated, multiple-view visualization for our computer architecture simulation and exploration environment, called Sesame, which aims at system-level performance analysis and design space exploration of multi-core embedded systems. Our results show that our multivariate visualization support can help designers to more easily understand the reasons behind the differences in performance of different design choices, and thus gain more insight in the performance landscape of the design space.

System-level MP-SoC design space exploration using tree visualization

Abstract: The complexity of today's embedded systems forces designers to model and simulate systems and their components to explore the wide range of design choices. Such design space exploration is especially needed during the early design stages, where the design space is at its largest. Due to the exponential design space in real problems, evaluating and comparing every single point in the design space is infeasible. Therefore, heuristic search techniques, such as Evolutionary Algorithms (EA), are often used to search the design space for optimum design points using only a finite number of design-point evaluations. Understanding how the design space was searched by such searching algorithms and providing insight into the “landscape” of the design space, may be of invaluable importance to the designer, To this end, this paper presents a novel interactive visualization application, based on tree visualization, to understand the search dynamics of an evolutionary algorithm and to visualize where the optimum design points are located in the design space.

Design metrics and visualization techniques for analyzing the performance of MOEAs in DSE

Abstract: VMODEX is an interactive visualization tool to support system-level Design Space Exploration (DSE) of MPSoC architectures. It was initially developed to help designers to get insight into the search process of Multi-Objective Evolutionary Algorithms (MOEAs) that are typically used in the DSE process, and facilitates the analysis of the DSE results. In this paper, we extend VMODEX to help algorithm developers as well. Since there are many different MOEAs to search a design space and there is no conclusive answer regarding which algorithm is the best for a specific problem, finding the best optimization algorithm is a big challenge. However, using VMODEX, algorithm developers can easily evaluate and compare the results of different searching algorithms, for a given problem, with respect to their efficiency and effectiveness, in order to find the best optimization algorithm. Then, the best optimization results are delivered to the designers for analyzing the design space exploration process.

Design space pruning through hybrid analysis in system-level design space exploration

Abstract: System-level design space exploration (DSE), which is performed early in the design process, is of eminent importance to the design of complex multi-processor embedded system architectures. During system-level DSE, system parameters like, e.g., the number and type of processors, the type and size of memories, or the mapping of application tasks to architectural resources, are considered. Simulation-based DSE, in which different design instances are evaluated using system-level simulations, typically are computationally costly. Even using high-level simulations and efficient exploration algorithms, the simulation time to evaluate design points forms a real bottleneck in such DSE. Therefore, the vast design space that needs to be searched requires effective design space pruning techniques. This paper presents a technique to reduce the number of simulations needed during system-level DSE. More specifically, we propose an iterative design space pruning methodology based on static throughput analysis of different application mappings. By interleaving these analytical throughput estimations with simulations, our hybrid approach can significantly reduce the number of simulations that are needed during the process of DSE.

Greenhouse Monitoring and Control System Based on Zigbee Wireless Senor Network

Abstract: For the sake of overcoming the shortcoming of the wired system such as complex wiring and low anti-interference capacity, a wireless measurement and control system for greenhouse is developed based on Zigbee, which is composed of upper monitor control PC, wireless gateway CC2430, sensor node CC2430 and sensor module. The star network topology is adopted on the basis of studying the characteristic of the control system for greenhouse. The wireless sensor network with tree topology structure is made up of a center controller and six wireless sensor nodes, and then the node hardware circuit is designed including temperature sensors, humidity sensors and illuminance sensors. The wireless module software is programmed by C language in IAR Embedded Workbench for MCS-51 Evaluation, and furthermore, the user interface software is developed based on Visual C++ 6.0 in windows. The test is done in 70m×10m greenhouse where six wireless sensor nodes are evenly distributed, which shows that the measure error of the temperature, humidity, illuminance is within 3%.

Visualization of Multi-objective Design Space Exploration for Embedded Systems

Abstract: Modern embedded systems come with contradictory design constraints. On one hand, these systems often target mass production and battery-based devices, and therefore should be cheap and power efficient. On the other hand, they need to achieve high (real-time) performance. This wide spectrum of design requirements leads to complex heterogeneous system-on-chip (SoC) architectures. The complexity of embedded systems forces designers to model and simulate systems and their components to explore the wide range of design choices. Such design space exploration is especially needed during the early design stages, where the design space is at its largest. Due to the exponential design space in real problems and multiple criteria to be considered, multi-objective evolutionary algorithms (MOEAs) are often used to trim down a large design space into a finite set of points and provide the designer a set of tradable solutions with respect to the design criteria. Interpreting the search results (e.g., where are the Pareto points located), understanding their relations and analyzing how the design space was searched by such searching algorithms is of invaluable importance to the designer. To this end, this paper presents a novel interactive visualization tool, based on tree visualization, to understand the search dynamics of a MOEA and to visualize where the optimum design points are located in the design space and what objective values they have.

A comparative evaluation of multi-objective exploration algorithms for high-level design

Abstract: This article presents a detailed overview and the experimental comparison of 15 multi-objective design-space exploration (DSE) algorithms for high-level design. These algorithms are collected from recent literature and include heuristic, evolutionary, and statistical methods. To provide a fair comparison, the algorithms are classified according to the approach used and examined against a large set of metrics. In particular, the effectiveness of each algorithm was evaluated for the optimization of a multiprocessor platform, considering initial setup effort, rate of convergence, scalability, and quality of the resulting optimization. Our experiments are performed with statistical rigor, using a set of very diverse benchmark applications (a video converter, a parallel compression algorithm, and a fast Fourier transformation algorithm) to take a large spectrum of realistic workloads into account. Our results provide insights on the effort required to apply each algorithm to a target design space, the number of simulations it requires, its accuracy, and its precision. These insights are used to draw guidelines for the choice of DSE algorithms according to the type and size of design space to be optimized.