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Toshiaki Yamanaka
Researcher at Hitachi
Publications - Â 108
Citations - Â 2781
Toshiaki Yamanaka is an academic researcher from Hitachi. The author has contributed to research in topics: CMOS & Static random-access memory. The author has an hindex of 28, co-authored 107 publications receiving 2764 citations. Previous affiliations of Toshiaki Yamanaka include Renesas Electronics.
Papers
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Journal ArticleDOI
A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic
Kazuo Yano,Toshiaki Yamanaka,Takashi Nishida,M. Saito,Katsuhiro Shimohigashi,Akihiro Shimizu +5 more
TL;DR: In this article, a complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path, which consists of complementary inputs/outputs, an nMOS pass transistor logic network, and CMOS output inverters, and is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality.
Journal ArticleDOI
A 1.5-ns 32-b CMOS ALU in double pass-transistor logic
Suzuki Makoto,Norio Ohkubo,T. Shinbo,Toshiaki Yamanaka,Akihiro Shimizu,Katsuro Sasaki,Y. Nakagome +6 more
TL;DR: A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path and the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU.
Journal ArticleDOI
A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer
Norio Ohkubo,Suzuki Makoto,T. Shinbo,Toshiaki Yamanaka,Akihiro Shimizu,K. Sasaki,Y. Nakagome +6 more
TL;DR: A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology and a new 4-2 compressor and a carry lookahead adder (CLA) have been developed to enhance the speed performance.
Patent
SRAM having load transistor formed above driver transistor
Shuji Ikeda,Satoshi Meguro,Soichiro Hashiba,Isamu Kuramoto,Atsuyoshi Koike,Katsuro Sasaki,Koichiro Ishibashi,Toshiaki Yamanaka,Naotaka Hashimoto,Nobuyuki Moriwaki,Shigeru Takahashi,Atsushi Hiraishi,Yutaka Kobayashi,Yukutake Seigo +13 more
TL;DR: In this article, a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFs.
Patent
Method of forming a pattern
Toshihiko Tanaka,Norio Hasegawa,Toshiaki Yamanaka,Akira Imai,Hiroshi Shiraishi,Takumi Ueno,Hiroshi Fukuda +6 more
TL;DR: In this paper, a comb-like or dot-like phase shifter pattern is added to a phase shift mask, which is then exposed onto a wafer to create extremely fine line patterns or space patterns.