Millimeter-wave (mmW) frequencies between 30 and 300 GHz are a new frontier for cellular communication that offers the promise of orders of magnitude greater bandwidths combined with further gains via beamforming and spatial multiplexing from multielement antenna arrays. This paper surveys measurements and capacity studies to assess this technology with a focus on small cell deployments in urban environments. The conclusions are extremely encouraging; measurements in New York City at 28 and 73 GHz demonstrate that, even in an urban canyon environment, significant non-line-of-sight (NLOS) outdoor, street-level coverage is possible up to approximately 200 m from a potential low-power microcell or picocell base station. In addition, based on statistical channel models from these measurements, it is shown that mmW systems can offer more than an order of magnitude increase in capacity over current state-of-the-art 4G cellular networks at current cell densities. Cellular systems, however, will need to be significantly redesigned to fully achieve these gains. Specifically, the requirement of highly directional and adaptive transmissions, directional isolation between links, and significant possibilities of outage have strong implications on multiple access, channel structure, synchronization, and receiver design. To address these challenges, the paper discusses how various technologies including adaptive beamforming, multihop relaying, heterogeneous network architectures, and carrier aggregation can be leveraged in the mmW context.

Millimeter-Wave Cellular Wireless Networks: Potentials and Challenges

Communication at millimeter wave (mmWave) frequencies is defining a new era of wireless communication. The mmWave band offers higher bandwidth communication channels versus those presently used in commercial wireless systems. The applications of mmWave are immense: wireless local and personal area networks in the unlicensed band, 5G cellular systems, not to mention vehicular area networks, ad hoc networks, and wearables. Signal processing is critical for enabling the next generation of mmWave communication. Due to the use of large antenna arrays at the transmitter and receiver, combined with radio frequency and mixed signal power constraints, new multiple-input multiple-output (MIMO) communication signal processing techniques are needed. Because of the wide bandwidths, low complexity transceiver algorithms become important. There are opportunities to exploit techniques like compressed sensing for channel estimation and beamforming. This article provides an overview of signal processing challenges in mmWave wireless systems, with an emphasis on those faced by using MIMO communication at higher carrier frequencies.

An Overview of Signal Processing Techniques for Millimeter Wave MIMO Systems

With the severe spectrum shortage in conventional cellular bands, millimeter wave (mmW) frequencies between 30 and 300 GHz have been attracting growing attention as a possible candidate for next-generation micro- and picocellular wireless networks. The mmW bands offer orders of magnitude greater spectrum than current cellular allocations and enable very high-dimensional antenna arrays for further gains via beamforming and spatial multiplexing. This paper uses recent real-world measurements at 28 and 73 GHz in New York, NY, USA, to derive detailed spatial statistical models of the channels and uses these models to provide a realistic assessment of mmW micro- and picocellular networks in a dense urban deployment. Statistical models are derived for key channel parameters, including the path loss, number of spatial clusters, angular dispersion, and outage. It is found that, even in highly non-line-of-sight environments, strong signals can be detected 100-200 m from potential cell sites, potentially with multiple clusters to support spatial multiplexing. Moreover, a system simulation based on the models predicts that mmW systems can offer an order of magnitude increase in capacity over current state-of-the-art 4G cellular networks with no increase in cell density from current urban deployments.

http://apps.fcc.gov/ecfs/document/view;NEWECFSSESSION=ThTmVg1SGvsFqgxGKYfckQC26BmBGYLH2jpL5z0dMms1j21m5YTC!-1110365353!-349327291?id=60001013324

Millimeter Wave Channel Modeling and Cellular Capacity Evaluation

There is considerable pressure to define the key requirements of 5G, develop 5G standards, and perform technology trials as quickly as possible. Normally, these activities are best done in series but there is a desire to complete these tasks in parallel so that commercial deployments of 5G can begin by 2020. 5G will not be an incremental improvement over its predecessors; it aims to be a revolutionary leap forward in terms of data rates, latency, massive connectivity, network reliability, and energy efficiency. These capabilities are targeted at realizing high-speed connectivity, the Internet of Things, augmented virtual reality, the tactile internet, and so on. The requirements of 5G are expected to be met by new spectrum in the microwave bands (3.3-4.2 GHz), and utilizing large bandwidths available in mm-wave bands, increasing spatial degrees of freedom via large antenna arrays and 3-D MIMO, network densification, and new waveforms that provide scalability and flexibility to meet the varying demands of 5G services. Unlike the one size fits all 4G core networks, the 5G core network must be flexible and adaptable and is expected to simultaneously provide optimized support for the diverse 5G use case categories. In this paper, we provide an overview of 5G research, standardization trials, and deployment challenges. Due to the enormous scope of 5G systems, it is necessary to provide some direction in a tutorial article, and in this overview, the focus is largely user centric, rather than device centric. In addition to surveying the state of play in the area, we identify leading technologies, evaluating their strengths and weaknesses, and outline the key challenges ahead, with research test beds delivering promising performance but pre-commercial trials lagging behind the desired 5G targets.

5G : A tutorial overview of standards, trials, challenges, deployment, and practice

With the explosive growth of mobile data demand, the fifth generation (5G) mobile network would exploit the enormous amount of spectrum in the millimeter wave (mmWave) bands to greatly increase communication capacity. There are fundamental differences between mmWave communications and existing other communication systems, in terms of high propagation loss, directivity, and sensitivity to blockage. These characteristics of mmWave communications pose several challenges to fully exploit the potential of mmWave communications, including integrated circuits and system design, interference management, spatial reuse, anti-blockage, and dynamics control. To address these challenges, we carry out a survey of existing solutions and standards, and propose design guidelines in architectures and protocols for mmWave communications. We also discuss the potential applications of mmWave communications in the 5G network, including the small cell access, the cellular access, and the wireless backhaul. Finally, we discuss relevant open research issues including the new physical layer technology, software-defined network architecture, measurements of network state information, efficient control mechanisms, and heterogeneous networking, which should be further investigated to facilitate the deployment of mmWave communication systems in the future 5G networks.

A survey of millimeter wave communications (mmWave) for 5G: opportunities and challenges

A 0.13-mum SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P1dB of 10 to 12dBm, Psat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated

A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications

A low-noise amplifier, direct-conversion quadrature mixer, power amplifier, and voltage-controlled oscillators have been implemented in a 012-/spl mu/m, 200-GHz f/sub T/290-GHz f/sub MAX/ SiGe bipolar technology for operation at 60 GHz At 615 GHz, the two-stage LNA achieves 45-dB NF, 15-dB gain, consuming 6 mA from 18 V This is the first known demonstration of a silicon LNA at V-band The downconverter consists of a preamplifier, I/Q double-balanced mixers, a frequency tripler, and a quadrature generator, and is again the first known demonstration of silicon active mixers at V-band At 60 GHz, the downconverter gain is 186 dB and the NF is 133 dB, and the circuit consumes 55 mA from 27 V, while the output buffers consume an additional 52 mA The balanced class-AB PA provides 108-dB gain, +112-dBm 1-dB compression point, 43% maximum PAE, and 16-dBm saturated output power Finally, fully differential Colpitts VCOs have been implemented at 22 and 67 GHz The 67-GHz VCO has a phase noise better than -98 dBc/Hz at 1-MHz offset, and provides a 31% tuning range for 8-mA current consumption from a 3-V supply

SiGe bipolar transceiver circuits operating at 60 GHz

An integrated SiGe superheterodyne RX/TX pair capable of Gb/s data rates in the 60GHz band is described. The 6dB NF RX includes an image-reject LNA, a multistage down-converter with on-chip IF filters, a frequency tripler, a PLL, and baseband outputs. The 10 to 12dBm P1dBTX achieves 10% PAE in the final stage. It includes a PA, image-reject driver, multistage up-converter with on-chip filters, tripler, and PLL

A silicon 60GHz receiver and transmitter chipset for broadband communications

This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feedback equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200mVppd, one transmitter/receiver pair and one PLL consume 300mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

A 4.9-6.4-Gb/s two-level SerDes ASIC I/O core employing a four-tap feed-forward equalizer (FFE) in the transmitter and a five-tap decision-feedback equalizer (DFE) in the receiver has been designed in 0.13-/spl mu/m CMOS. The transmitter features a total jitter (TJ) of 35 ps p-p at 10/sup -12/ bit error rate (BER) and can output up to 1200 mVppd into a 100-/spl Omega/ differential load. Low jitter is achieved through the use of an LC-tank-based VCO/PLL system that achieves a typical random jitter of 0.6 ps over a phase noise integration range from 6 MHz to 3.2 GHz. The receiver features a variable-gain amplifier (VGA) with gain ranging from -6to +10dB in /spl sim/1dB steps, an analog peaking amplifier, and a continuously adapted DFE-based data slicer that uses a hybrid speculative/dynamic feedback architecture optimized for high-speed operation. The receiver system is designed to operate with a signal level ranging from 50 to 1200 mVppd. Error-free operation of the system has been demonstrated on lossy transmission line channels with over 32-dB loss at the Nyquist (1/2 Bd rate) frequency. The Tx/Rx pair with amortized PLL power consumes 290 mW of power from a 1.2-V supply while driving 600 mVppd and uses a die area of 0.79 mm/sup 2/.

Troy J. Beukema

Papers

A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications

SiGe bipolar transceiver circuits operating at 60 GHz

A silicon 60GHz receiver and transmitter chipset for broadband communications

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization