..................................................................................................... 90 KOKKUVÕTE .................................................................................................. 92 ACKNOWLEDGEMENTS ............................................................................... 94 Appendix A ........................................................................................................ 95 Appendix B ...................................................................................................... 103 Appendix C ...................................................................................................... 109 Appendix D ...................................................................................................... 117 Appendix E ...................................................................................................... 125 Appendix F ...................................................................................................... 133

Comprehensive Abstraction of VHDL RTL Cores to ESL SystemC

Driven by flexibility, performance and cost constraints of demanding modern applications, heterogeneous System-on-Chip (SoC) is the dominant design paradigm in the embedded system computing domain. SoC architecture and heterogeneity clearly provide a wider power/performance scaling, combining high performance and power efficient general-purpose cores along with massively parallel many-core-based accelerators. Besides the complex hardware, generally these kinds of platforms host also an advanced software ecosystem, composed by an operating system, several communication protocol stacks, and various computational demanding user applications. The necessity to efficiently cope with the hugeHW/SW design space provided by this scenario makes clearly full-system simulator one of the most important design tools. We present in this paper a new emulation framework, called Virtual SoC, targeting the full-system simulation of massively parallel heterogeneous SoCs.

VirtualSoC: A Full-System Simulation Environment for Massively Parallel Heterogeneous System-on-Chip

Cyber-physical systems (CPS) tightly integrate cyber and physical components and transcend discrete and continuous domains. It is greatly desired that the synergy between cyber and physical components of CPS is explored even before the complete system is put together. Virtualization has potential to play a significant role in exploring such synergy. In this paper, we propose a CPS virtualization approach based on the integration of virtual machine and physical component emulator. It enables real software, virtual hardware, and virtual physical components to execute in a holistic virtual execution environment. We have implemented this approach using QEMU as the virtual machine and Matlab/Simulink as the physical component emulator, respectively. To achieve high-fidelity between the real system and its virtualization, we have developed a strategy for synchronizing the virtual machine and the physical component emulator. To evaluate our approach, we have successfully applied it to real-world control systems. Experiments results have shown that our approach achieves high-fidelity in capturing dynamic behaviors of the entire system. This approach is promising in enabling early development of cyber components of CPS and early exploration of the synergy of cyber and physical components.

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High fidelity virtualization of cyber-physical systems

In this paper, we propose a cycle estimation methodology for fast instruction-level CPU emulators. This methodology suggests achieving accurate software performance estimation at high emulation speed by utilizing a two-phase pipeline scheduling process: a static pipeline scheduling phase performed off-line before runtime, followed by an accuracy refinement phase performed at runtime. The first phase delivers a pre-estimated CPU cycle count while limiting impact on the emulation speed. The second phase refines the pre-estimated cycle count to provide further accuracy. We implemented this methodology on Qemu and compared cycle counts with a physical ARM CPU. Our results show the efficiency of the trade-offs between emulation speed and cycle accuracy: cycle simulation error averages 10% while the emulation latency is 3.37 times that of original Qemu.

Fast cycle estimation methodology for instruction-level emulator

Case of ARM emulation optimization for offloading mechanisms in Mobile Cloud Computing

In this paper, we present a fast cycle-accurate instruction set simulator (CA-ISS) for system-on-chip development based on QEMU and SystemC. Even though most state-of-the-art commercial tools have tried very hard to provide all the levels of details to satisfy the different requirements of the software designer, the hardware designer, and even the system architect, the hardware/software co-simulation speed is dramatically slow when co-simulating the hardware models at the register-transfer level (RTL) with a full-fledged operating system (OS). Our experimental results show that the combination of QEMU and SystemC can make the co-simulation at the CA level much faster than the conventional RTL simulation, even with a full-fledged operating system up and running. Furthermore, the statistics indicate that with every instruction executed and every memory accessed since power-on traced at the CA level, it takes 28m15.804s on average to boot up a full-fledged Linux kernel, even on a personal computer. Compared to the kernel boot time reported by Xilinx and SiCortex, the proposed CA-ISS is about 6.09 times faster compared to “SystemC without trace” of Xilinx and about 30.32 times faster compared to “SystemC models converted from RTL” of SiCortex. The main contributions of this paper are threefold: 1) a hardware/software co-simulation environment capable of running a full-fledged OS at the early stage of the electronic system level design flow at an acceptable simulation speed is proposed; 2) a virtual platform constructed using the proposed CA-ISS as the processor model can be used to estimate the performance of a target system from system perspective, which all the previous works, such as QEMU-SystemC, do not provide; and 3) such a virtual platform also provides the modeling capability from the transaction level down to the CA level or the other way around.

A QEMU and SystemC-Based Cycle-Accurate ISS for Performance Estimation on SoC Development

This paper presents a fast cycle-accurate instruction set simulator (CA-ISS) based on QEMU and SystemC. The CA-ISS can be used for design space exploration and as the processor core for virtual platform construction at the cycle-accurate level. Even though most state-of-the-art commercial tools try to provide all the levels of details to satisfy the different requirements of the software designer, the hardware designer, or even the system architect, the hardware/software co-simulation speed is dramatically slow when co-simulating the hardware models at the register-transfer level with a full-fledged operating system. In this paper, we show that the combination of QEMU and SystemC can make the co-simulation at the cycle-accurate level extremely fast, even with a full-fledged operating system up and running. Our experimental results indicate that with every instruction executed and every memory accessed since power-on traced at the cycle-accurate level, it takes less than 17 minutes on average to boot up a full-fledged Linux kernel, even on a laptop.

A fast cycle-accurate instruction set simulator based on QEMU and SystemC for SoC development

On the interfacing between QEMU and SystemC for virtual platform construction: Using DMA as a case

In this paper, we present an interface for connecting the master/slave ports of hardware modeled in SystemC to a QEMU and SystemC based virtual platform. The virtual platform uses QEMU as the instruction-accurate instruction set simulator (IA-ISS) and is capable of running a full-fledged operating system such as Linux. The proposed interface enables the hardware modeled in SystemC to access hardware modeled in QEMU; thus, it can be used to facilitate the co-design of diverse hardware models and device drivers at the early stage of Electronic System Level (ESL) design flow. Our experimental results—of using Direct Memory Access Controller (DMAC) with two master ports and one slave port as an example—show that the proposed interface makes it possible for migrating hardware models from QEMU to SystemC and for cross verifying the hardware models and device drivers. Moreover, the virtual platform is capable of providing instruction-accurate statistics, thus making it easy for evaluating the performance of the hardware models and for design space exploration.

On the interface between QEMU and SystemC for hardware modeling

In this paper, we present a technique for optimizing the simulation speed of the QEMU and SystemC-based virtual platform.Most of the optimization methods for conventional instruction set simulator based virtual platforms focus on accelerating the simulator kernel. However, the bottleneck that affects the simulation speed of a virtual machine based virtual platform is not necessarily the simulator kernel.In order to better understand the bottleneck, we investigate the QEMU and SystemC-based virtual platform,by using it to boot up a full-fledged Linux with data movement via DMA controller model at the instruction-accurate and cycle-count-accurate levels. Based on the outcome, we propose a method to optimize its simulation speed. Compared to the original version, the optimized version can boost up the simulation speed of instruction-accurate simulator by a factor of 1.153 and the simulation speed of cycle-count-accurate simulator with different bus arbitration policies by a factor of 1.354 or 1.390,thus making the virtual platform even more suitable for electronic system level (ESL) design flow.

Tse-Chen Yeh

Papers

A QEMU and SystemC-Based Cycle-Accurate ISS for Performance Estimation on SoC Development

A fast cycle-accurate instruction set simulator based on QEMU and SystemC for SoC development

On the interfacing between QEMU and SystemC for virtual platform construction: Using DMA as a case

On the interface between QEMU and SystemC for hardware modeling

Optimizing the Simulation Speed of QEMU and SystemC-Based Virtual Platform