Tughrul Arslan

Bio: Tughrul Arslan is an academic researcher from University of Edinburgh. The author has contributed to research in topics: Field-programmable gate array & System on a chip. The author has an hindex of 31, co-authored 591 publications receiving 5378 citations. Previous affiliations of Tughrul Arslan include University of Wales & Cardiff University.

The Reconfigurable Instruction Cell Array

Abstract: This paper presents a novel instruction cell-based reconfigurable computing architecture for low-power applications, thereafter referred to as the reconfigurable instruction cell array (RICA). For the development of the RICA, a top-down software driven approach was taken and revealed as one of the key design decisions for a flexible, easy to program, low-power architecture. These features make RICA an architecture that inherently solves the main design requirements of modern low-power devices. Results show that it delivers considerably less power consumption when compared to leading VLIW and low-power digital signal processors, but still maintaining their throughput performance.

Evolvable Components: From Theory to Hardware Implementations

Abstract: 1 Introduction.- 1.1 Natural Computing.- 1.1.1 Soft Computing.- 1.1.2 Quantum Computing.- 1.1.3 DNA Computing.- 1.1.4 Membrane Computing.- 1.2 Bioinspired Hardware.- 1.3 Motivation for Research.- 2 Reconfigurable Hardware.- 2.1 Digital Cicuits.- 2.2 Digital Circuit Design.- 2.3 Field Programmable Gate arrays.- 2.3.1 Architecture of FPGAs.- 2.3.2 The XC4000 Family.- 2.3.3 ThE Virtex Family.- 2.3.4 The XC6200 Family.- 2.3.5 Atmel FPGAs.- 2.3.6 Features of FPGAs.- 2.4 Hardware Reused as Software.- 2.5 Reconfigurable Computing.- 2.6 Nanotechnology.- 2.7 Cell Matrix.- 2.8 Summary.- 3 Evolutionary Algorithms.- 3.1 Introduction.- 3.2 Variant of Evolutionary Algorithms.- 3.2.1 Genetic Algorithms.- 3.2.2 Genetic Programming.- 3.2.3 Evolutionary Strategies.- 3.2.4 Evolutionary Programming.- 3.3 Some Other Features of Evolutionary Algorithms.- 3.3.1 Parallel Implementations.- 3.3.2 Dynamic Fitness Function.- 3.4 Evolutionary Design and Optimization.- 3.5 The Evolutionary Algorithm Design.- 3.5.1 Missing Theories.- 3.5.2 The Design Strategies.- 3.6 Formal Approach.- 3.7 Summary.- 4 Evolvable Hardware.- 4.1 Basic Concept.- 4.2 Cartesian Genetic Programming.- 4.3 Features of Cartesian Genetic Programming.- 4.3.1 Redundancy and Neutrality.- 4.3.2 Fitness Landscape Analysis.- 4.3.3 Implementation Issues.- 4.4 From Chromosome to Fitness Value.- 4.4.1 Representation.- 4.4.2 Platforms for Circuit Evolution.- 4.4.3 Circuit Evaluation.- 4.5 Fitness Function.- 4.5.1 Fitness Function and Circuit Behavior.- 4.5.2 Evolutionary Circuit Design: Static Fitness Function.- 4.5.3 Evolvable Hardware: Dynamic Fitness Function.- 4.5.4 Discussion.- 4.6 Applications and Degree of Hardware Implementation.- 4.7 Promising Results.- 4.8 Major Current Problems and Potential Solutions.- 4.8.1 Scalability of Representaion.- 4.8.2 SCalability of Fitnes Evaluation.- 4.8.3 Robustness of the Evolved Circuits.- 4.8.4 Applications in Dynamic Environments.- 4.9 Summary.- 5 Towards Evolvable Components.- 5.1 Component Approach to Problem Solving.- 5.2 Evolvable Components.- 5.2.1 System Decomposition.- 5.2.2 Interface.- 5.3 Hardware Implementation.- 5.3.1 Evolvable Componenets.- 5.3.2 Environment.- 5.3.3 Communication Betweem Evolvable Component and Environment.- 5.4 Extension of Evolvable Components.- 5.5 Summary.- 6 Evolvable Computational Machines.- 6.1 Computational Machines and Evolutionary Design.- 6.2 Cellular Automata.- 6.2.1 Basic Model.- 6.2.2 Evolvable Non-Uniform CEllular Automaton.- 6.2.3 An example: Evolvable Non-Uniform Cellular Automaton as a Sequence Generator.- 6.3 General Evolvable Computational Machine.- 6.4 Dynamic Environment.- 6.5 Evolvable Computational System.- 6.5.1 Formal Definition.- 6.5.2 An example: Formal Description of a Simple Image Compression.- 6.6 Properties of Evolvable Machines.- 6.6.1 On the Computation of Evolvable Machines.- 6.6.2 Mappings g and f.- 6.6.3 Changing Fitness Fuction.- 6.7 The Computational Power.- 6.7.1 The Turing Machine and the Church Turing Thesis.- 6.7.2 Beyond the Turing Machines.- 6.7.3 A New Paradigm.- 6.7.4 Site Machine.- 6.7.5 the Power of an Evolvable System.- 6.7.6 Discussion.- 6.8 Summary.- 7 An Evolvable Component for Image Pre-processing.- 7.1 Motivation and Problem Specification.- 7.2 The Image Filter Design.- 7.2.1 Types of Noise Considered for Testing.- 7.2.2 Convnetional Approaches.- 7.2.3 Implementation of FPGAs.- 7.2.4 A Brief Survey of Evolutionary Approaches.- 7.3 Analysis of Reconfigurability and Size of the Search Space.- 7.3.1 Elementary Measures.- 7.3.2 Cartesian Genetic Programming in Hardware.- 7.3.3 Cartesian Genetic Programming at the Fuctional Level.- 7.4 Evolutionary Design: Experimental Framework.- 7.4.1 Reconfigurable Circuit.- 7.4.2 Evolutionary Algorithms.- 7.4.3 Fitness Function.- 7.5 Filters for Smoothing.- 7.5.1 The Results.- 7.5.2 Discussion.- 7.6 Other Image Operators.- 7.6.1 "Salt and Pepper" Noise Filters.- 7.6.2 Random Shot-Noise Filters.- 7.6.3 Edge Detectors.- 7.7 Dynamics Environment.- 7.7.1 Experimental Setup.- 7.7.2 The Results in Tables 7.9 and 7.10.- 7.7.3 Discussion.- 7.8 A Note on a Single Filter Design.- 7.9 Summary.- Virtual Reconfigurable Devices.- 8.1 Chip on Top of a Chip.- 8.2 Architecture of Virtual Reconfigurable Circuits.- 8.2.1 Overview.- 8.2.2 Routing Logic and Configuration Memory.- 8.2.3 Configuration Options.- 8.3 Implementation Costs.- 8.4 Speeding up the Evolutionary Design.- 8.5 Genetic Unit.- 8.6 Physical Realization.- 8.7 Discussion.- 8.8 Summary.- 9 Concluding Statements.- 9.1 The Approach.- 9.2 The Obtained Results.- 9.3 Future Work.- References.

An ILP formulation for task mapping and scheduling on multi-core architectures

Abstract: Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory architecture, and task mapping and scheduling. This paper presents an integer linear programming formulation for the task mapping and scheduling problem. The technique incorporates profiling-driven loop level task partitioning, task transformations, functional pipelining, and memory architecture aware data mapping to reduce system execution time. Experiments are conducted to evaluate the technique by implementing a series of DSP applications on several multi-core architectures based on dynamically reconfigurable processor cores. The results demonstrate that the proposed technique is able to generate high-quality mappings of realistic applications on the target multi-core architecture, achieving up to 1.3× parallel efficiency by employing only two dynamically reconfigurable processor cores.

Locating electromagnetic signal sources

Abstract: There is disclosed a method of estimating the location of a plurality of electromagnetic signal sources, comprising: scanning at a first plurality of locations to generate signal source position data, the signal source position data representing estimates of the position of at least one of said signal sources; scanning at a second plurality of locations using a signal detection system to generate signal detection data, the signal detection data relating to signals received at the second plurality of locations from the signal sources; processing the signal source position data in dependence on the signal detection data to correct estimation errors in the signal source position data; and outputting the processed signal source position data.

A novel coefficient ordering based low power pipelined radix-4 FFT processor for wireless LAN applications

Abstract: The FFT processor is a critical block in all multicarrier systems used primarily in the mobile environment. The portability requirement of these systems is mainly responsible for the need of low power FFT architectures. This paper proposes a technique to reduce the power consumption of a popular low power radix-4 pipelined FFT processor by modifying its operation sequence. The complex multiplier is one of the most power consuming blocks in the FFT processor. The switching activity at its fixed coefficient input, and hence its power consumption, can be drastically reduced by coefficient ordering. Coefficient ordering requires a novel commutator architecture which can handle the corresponding data sequencing as per new coefficient ordering. The resulting power saving is around 23% and 9%, respectively, for the 16-point and 64-point radix-4 pipelined FFT processor. This approach is very attractive for orthogonal frequency division multiplexing (OFDM) based wireless LAN (IEEE 802.11) requiring short FFTs but it can also be applied to the penultimate stage of longer FFTs used in digital audio and video broadcasting.

Evolutionary algorithms for solving multi-objective problems

Abstract: List of Figures. List of Tables. Preface. Foreword. 1. Basic Concepts. 2. Evolutionary Algorithm MOP Approaches. 3. MOEA Test Suites. 4. MOEA Testing and Analysis. 5. MOEA Theory and Issues. 3. MOEA Theoretical Issues. 6. Applications. 7. MOEA Parallelization. 8. Multi-Criteria Decision Making. 9. Special Topics. 10. Epilog. Appendix A: MOEA Classification and Technique Analysis. Appendix B: MOPs in the Literature. Appendix C: Ptrue & PFtrue for Selected Numeric MOPs. Appendix D: Ptrue & PFtrue for Side-Constrained MOPs. Appendix E: MOEA Software Availability. Appendix F: MOEA-Related Information. Index. References.

Wireless Networks With RF Energy Harvesting: A Contemporary Survey

Abstract: Radio frequency (RF) energy transfer and harvesting techniques have recently become alternative methods to power the next-generation wireless networks As this emerging technology enables proactive energy replenishment of wireless devices, it is advantageous in supporting applications with quality-of-service requirements In this paper, we present a comprehensive literature review on the research progresses in wireless networks with RF energy harvesting capability, which is referred to as RF energy harvesting networks (RF-EHNs) First, we present an overview of the RF-EHNs including system architecture, RF energy harvesting techniques, and existing applications Then, we present the background in circuit design as well as the state-of-the-art circuitry implementations and review the communication protocols specially designed for RF-EHNs We also explore various key design issues in the development of RF-EHNs according to the network types, ie, single-hop networks, multiantenna networks, relay networks, and cognitive radio networks Finally, we envision some open research directions

A Field Guide to Genetic Programming

Abstract: Genetic programming (GP) is a systematic, domain-independent method for getting computers to solve problems automatically starting from a high-level statement of what needs to be done. Using ideas from natural evolution, GP starts from an ooze of random computer programs, and progressively refines them through processes of mutation and sexual recombination, until high-fitness solutions emerge. All this without the user having to know or specify the form or structure of solutions in advance. GP has generated a plethora of human-competitive results and applications, including novel scientific discoveries and patentable inventions. This unique overview of this exciting technique is written by three of the most active scientists in GP. See www.gp-field-guide.org.uk for more information on the book.

Neuromorphic Silicon Neuron Circuits

Abstract: Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin-Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.