U. Kleine

Abstract: This paper describes a novel analog module generator environment for the automatic layout development of analog circuits. The C++ tool features a novel procedural layout description language that drastically eases the creation of analog modules. Due to the object oriented programming the designer can specify the modules in a hierarchical way using elementary geometrical primitives and conditional statements. The primitive objects are placed relatively and are abutted with the help of a special compactor. An optimization routine with backtracking capability facilitates the creation of high quality analog layouts. A layout example of a broad-band BiCMOS amplifier will demonstrate the usability of the tool.

Abstract: This paper presents a new feature for a module generator environment that performs application independent module description in analog layouts. With the help of a special capacitance sensitivity matrix one module description can be used for different applications.

Abstract: Analog macrocell placement is an NP-hard problem. This paper presents an attempt to solve this problem by using the optimization flow of a genetic algorithm (GA) enhanced by simulated annealing (SA). The bit-matrix representation is employed to improve the search efficiency. In particular, to reduce the solution space without degrading search opportunities, the technique of cell slide is deployed to transform an absolute placement to a relative placement. Following this cell-slide process, it is proved that, for an initial placement, there always exists a solution that can guarantee no occurrence of overlaps among cells and meet any applicable symmetry constraints pertaining to analog layouts. For the optimization of the algorithm parameters, the fractional factorial experiment using an orthogonal array has been conducted, and the exact parameter values are determined using a meta-GA approach. The experimental results show that, compared with the SA approach, the proposed algorithm consumes less computation time while generating higher quality layouts, comparable to expert manual placements

Abstract: In this paper the design of a CMOS cascoded operational amplifier is described. Due to technology scaling the design of a former developed operational amplifier has now overcome its stability problems. A stable three stage operational amplifier is presented. A layout has been created automatically by using the ALADIN tool. With help of the extracted layout the performance data of the amplifier is simulated.

Abstract: This paper presents a new description language and a graphical user interface for a module generator environment. The description language MOGLAN is adapted to the problem of writing analog module generators and provides an easy-to-read, short source code. The graphical user interface supports the writing, translating, executing, and debugging of modules. With these tools, analog designers are able to write module generators and to bring in their analog specific knowledge. This increases the quality of automatic layout solutions and decreases the time consuming process of manual layout generation.

Abstract: This paper presents a new design assistant for analog integrated circuits. The interactive tool is implemented in the Design Framework II of Cadence and supports the designer during circuit design. With the help of this new assistant analog designers can create ad hoc layouts of their circuits. These layouts are automatically extracted, and the updated netlist of the circuit is used for further simulation and optimization steps. Thus the optimization is speeded up and the reliability of the design is improved due to the more accurate modeling of the parasitic circuit elements. The use of the design assistant will be demonstrated by various examples.

Abstract: Practical analog layout synthesis techniques have been the subject of active research for the past two decades to address the growing gap between the increasing chip functionality and the design productivity. In this paper, we present a novel macro-cell placement approach following the optimization flow of a genetic algorithm controlled by the methodology of simulated annealing. A process of cell slide is adopted to drastically reduce the configuration space without degrading search opportunities. In addition, this cell-slide process is used to satisfy the symmetry constraints essential for analog layouts. Furthermore, the dedicated cost function captures subtle electrical and geometrical constraints, such as area, net length, aspect ratio, proximity, parasitic effects, etc. required for analog layout and subsequent intellectual property reuse. To study the algorithm parameters, fractional factorial experiments and a meta-GA approach are employed. The proposed algorithm has been tested using several analog circuits. Compared to the simulated-annealing approach, the dominant one currently used for the analog placement problem, the proposed algorithm requires less computation time while generating higher quality layouts, comparable to expert manual placements. Furthermore, our hybrid algorithm and the method of parameter optimization can be readily adapted to different optimization problems across disciplines.