Accurate modeling of MOS devices requires quantitative knowledge of carrier mobilities in surface inversion and accumulation layers. Optimization of device structures and accurate circuit simulation, particulary as technologies push toward fundamental limits, necessitate an understanding of how impurity doping levels, oxide charge densities, process techniques, and applied electric fields affect carrier surface mobilities. It is the purpose of this paper to present an extensive set experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures. Empirical equations are developed which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions. The experimental results are interpreted in terms of the dominant physical mechanisms responsible for mobility degradation at the Si/SiO 2 interface. From the observed effects of process parameters on mobility roll-off under high vertical fields, conclusions are drawn about optimum process conditions for maximizing mobility. The implications of this work for performance limits of several types of MOS devices are described.

Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces

ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

Semiconductor Power Devices

Accurate modeling of MOS devices requires quantitative knowledge of carrier mobilities in surface inversion and accumulation layers. Optimization of device structures and accurate circuit simulation, particularly as technologies push toward fundamental limits, necessitate an understanding of how impurity doping levels, oxide charge densities, process techniques, and applied electric fields affect carrier surface nobilities. It is the purpose of this paper to present an extensive set of experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures. EmpiricaI equations are developed which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions. The experimental results are interpreted in terms of the dominant physical mechanisms responsible for mobility degradation at the Si/SiO/sub 2/ interface. From the observed effects of process parameters on mobility roll-off under high vertical fields, conclusions are drawn about optimum process conditions for maximizing mobility. The implications of this work for performance limits of several types of MOS devices are described.

Electron Mobility in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces

Power MOS transistors have recently begun to rival bipolar devices in power-handling capability. This new capability has arisen primarily through the use of double-diffusion techniques to achieve short active channels and the incorporation of a lightly doped drift region between the channel and the drain contact, which largely supports the applied voltage. Many different structures have been proposed to implement these new devices. This paper considers three of the most common-LDMOS, VDMOS, and VMOS. Structural differences which result in on-resistance and transconductance differences between the devices are described. Quantitative models, suitable for device design, are developed for the on-resistance of each type of structure. These models are developed directly from the physical structure (geometry and doping profiles) so that they are useful in optimizing a particular device structure or in quantitatively comparing structures for a particular application.

Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors

A rapid type of second breakdown observed in silicon n+-p-n-n+transistors is shown to be due to avalanche injection at the collector n-n+junction. Localized thermal effects, which are usually associated With second breakdown, are shown to play a minor role in the initiation of the transition to the low voltage state. A useful tool in the analysis of avalanche injection is the n+-n-n+diode, which exhibits negative resistance at a critical voltage and current. A close correspondence between the behavior of the diode and the transistor (open base) is established both theoretically and experimentally. Qualitative agreement with the proposed model is obtained for both directions of base current flow. It is shown that transistors having thin, lightly doped collector regions are particularly susceptible to avalanche injection, which suggests that some compromise may be necessary in the design of high-frequency power transistors.

Avalanche injection and second breakdown in transistors

A method of evaluation of majority carrier field-effect mobilities in surface space charge regions is described. This method is also adapted for the determination of chargeable (fast) surface state distribution in the gap. Experimental results obtained with both p- and n-type thermally oxidized silicon samples are presented. In these samples, the surface state density was found to be less than 1010electronic states/cm2and thus were well suited for the evaluation of effective surface mobility by the dc field-effect measurements. The experimental mobilities are compared with those predicted by the theory of Greene et al. It was found that at flatband and at weak surface accumulation, measured values were lower than those theoretically predicted. For the case of strong surface accumulation, the opposite was true.

V.G. Krishna Reddi

Papers

Avalanche injection and second breakdown in transistors

Majority carrier surface mobilities in thermally oxidized silicon