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Author

V. Hariharan

Other affiliations: Shiv Nadar University
Bio: V. Hariharan is an academic researcher from Indian Institute of Technology Bombay. The author has contributed to research in topics: Velocity saturation & Materials science. The author has an hindex of 2, co-authored 5 publications receiving 30 citations. Previous affiliations of V. Hariharan include Shiv Nadar University.

Papers
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Journal ArticleDOI
TL;DR: In this article, a drain current model is developed for a symmetrically driven undoped (or lightly doped) symmetric double-gate MOSFET (SDGFET) under the drift-diffusion transport mechanism, with velocity saturation effects being included as an integral part of the model derivation.
Abstract: A drain current model is developed for a symmetrically driven undoped (or lightly doped) symmetric double-gate MOSFET (SDGFET) under the drift-diffusion transport mechanism, with velocity saturation effects being included as an integral part of the model derivation. Velocity saturation effects are modeled by using the Caughey-Thomas engineering model with exponent n = 2. Id-Vd, Id-Vg, gm -Vg, and gDS-Vd comparisons are made with 2-D device simulation results, and a very good match is found all the way from subthreshold to strong inversion. Gummel symmetry compliance is also shown.

22 citations

Journal ArticleDOI
27 Apr 2007
TL;DR: Parasitic resistance and capacitance relating to spacer region of FinFETs were investigated by changing shape of the spacer regions in this paper, where the trade-off relationship between these two parasitic elements was demonstrated on the expansion of the fin width in the Spacer region.
Abstract: Parasitic resistance and capacitance relating to spacer region of FinFETs were investigated by changing shape of the spacer region. The trade-off relationship between these two parasitic elements was demonstrated on the expansion of the fin width in the spacer region. The gate delay characteristic of the FinFETs was optimized by gradual expansion with triangular shape. It was indicated that not only parasitic resistance but also parasitic capacitance on the spacer region was significant for transistor performance.

4 citations

Proceedings ArticleDOI
01 Dec 2007
TL;DR: In this paper, a single-equation inversion-charge-based drain current model for SDGFETs based on the drift-diffusion transport mechanism using an exponent n=2 for velocity saturation was presented.
Abstract: In this paper we present for the first time a single-equation inversion-charge-based drain current model for SDGFETs based on the drift-diffusion transport mechanism using an exponent n=2 for velocity saturation, that is neither threshold voltage-based nor charge-sheet-based. Because it is not based on any charge sheet models, it automatically models phenomena specific to ultra-thin DGFETs such as volume inversion. We present the model equations and the final results showing analytical versus 2D device simulation results.

2 citations

Journal ArticleDOI
TL;DR: In this article, the authors presented an enhancement to an existing approximation for the value of an intermediate variable beta to the gate and drain voltages of a symmetric double-gate MOSFET.
Abstract: In developing the drain current model of a symmetric double-gate MOSFET, one encounters a transcendental equation relating the value of an intermediate variable beta to the gate and drain voltages. In this brief, we present an enhancement to an existing approximation for beta, which improves its numerical robustness. We also benchmark our suggested enhancement and show that our enhancement is as computationally efficient as the original approximation but is numerically much more robust, with an accuracy that is comparable to the original approximation.

1 citations


Cited by
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Journal ArticleDOI
TL;DR: In this paper, the influence of hot-carrier degradation effects on the drain current of a gate-stack double-gate (GS DG) MOSFET was studied by using an accurate continuous current?voltage (I?V) model, derived based on both Poisson's and continuity equations without the need of charge-sheet approximation.
Abstract: We have studied the influence of hot-carrier degradation effects on the drain current of a gate-stack double-gate (GS DG) MOSFET device. Our analysis is carried out by using an accurate continuous current?voltage (I?V) model, derived based on both Poisson's and continuity equations without the need of charge-sheet approximation. The developed model offers the possibility to describe the entire range of different regions (subthreshold, linear and saturation) through a unique continuous expression. Therefore, the proposed approach can bring considerable enhancement at the level of multi-gate compact modeling including hot-carrier degradation effects.

29 citations

Journal ArticleDOI
TL;DR: In this paper, a Monte Carlo event generator for the simulation of QCD-instanton induced processes in deep-inelastic scattering (HERA) is described. But this generator is designed as an ''add-on'' hard process generator interfaced to the general hadronic event simulation package HERWIG.
Abstract: We describe a Monte Carlo event generator for the simulation of QCD-instanton induced processes in deep-inelastic scattering (HERA). The QCDINS package is designed as an ``add-on'' hard process generator interfaced to the general hadronic event simulation package HERWIG. It incorporates the theoretically predicted production rate for instanton-induced events as well as the essential characteristics that have been derived theoretically for the partonic final state of instanton-induced processes: notably, the flavour democratic and isotropic production of the partonic final state, energy weight factors different for gluons and quarks, and a high average multiplicity O(10) of produced partons with a Poisson distribution of the gluon multiplicity. While the subsequent perturbative evolution of the generated partons is always handled by the HERWIG package, the final hadronization step may optionally be performed also by means of the general hadronic event simulation package JETSET.

28 citations

Journal ArticleDOI
TL;DR: In this paper, an analytic drain current model is presented for doped short-channel double-gate MOSFETs with a Gaussian-like doping profile in the vertical direction of the channel.
Abstract: An analytic drain current model is presented for doped short-channel double-gate MOSFETs with a Gaussian-like doping profile in the vertical direction of the channel. The present model is valid in linear and saturation regions of device operation. The drain current variation with various device parameters has been demonstrated. The model is made more physical by incorporating the channel length modulation effect. Parameters like transconductance and drain conductance that are important in assessing the analog performance of the device have also been formulated. The model results are validated by numerical simulation results obtained by using the commercially available ATLAS™, a two dimensional device simulator from SILVACO.

17 citations

Journal ArticleDOI
TL;DR: In this paper, a compact model for undoped short-channel cylindrical surrounding-gate MOSFETs is presented, where the drain-current model is expressed as a function of the mobile charge density, which is calculated using the analytical expressions of the surface potential and the difference between surface and center potentials model.
Abstract: In this paper, we present a compact model for undoped short-channel cylindrical surrounding-gate MOSFETs. The drain-current model is expressed as a function of the mobile charge density, which is calculated using the analytical expressions of the surface potential and the difference between surface and center potentials model. The short-channel effects are well incorporated in the drain-current model, such as the drain-induced barrier lowering, the charge sharing effect (VT Roll-off), the subthreshold slope degradation, and the channel length modulation. A comparison of the model results with 3D numerical simulations using Silvaco Atlas-TCAD presents a good agreement from subthreshold to strong inversion regime and for different bias voltages.

16 citations