Showing papers by "V. Kamakoti published in 2003"

Dynamic coding technique for low-power data bus

Abstract: Designing chips for lower power applications is one of the most important challenges faced by the VLSI designers. Since the power consumed by I/O pins of a CPU is a significant source of power consumption, work has been done on developing encoding schemes for reducing switching activity on external buses. In this paper we propose a new coding technique, namely, the Dynamic Coding Scheme, for low-power data bus. Our method considers two logical groupings of the bus lines, each being a permutation of the bus lines, and dynamically selects that grouping which yields the minimum number of transitions.

A parallel genetic approach to the placement problem for field programmable gate arrays

Abstract: This paper introduces the concept of "parallel genetic algorithms", to provide a solution for the placement problem for field programmable gate arrays, that complements routing to enhance the performance of the circuit implemented by the field programmable gate array. We propose to utilize the concept of parallelism to genetic algorithms to transform a set of initial populations of random placements to a final set of populations that contain solutions approximating the optimal one. The fundamental concept of this paper lies in sharing the good solutions among different processes, which may help the genetic algorithm to evolve its population in a more lucrative manner. In conjunction with the migration phase, we employ various genetic operators and the chosen fitness function, to expedite the transformation of the initial population towards the optimal solution. We have simulated the suggested method on a 64-node SGI Origin-2000 platform and the results are extremely encouraging, even for circuits with very large number of nets.

Parallel partitioning techniques for logic minimization using redundancy identification

Abstract: Redundancy identification is a challenging open problem in logic optimization of Boolean circuits. Partitioning techniques are employed successfully to solve the redundancy identification problem with less time and higher scalability. Any heuristic/algorithm for the Logic optimization problem, and hence the redundancy identification problem is compute-intensive, especially when very high approximation to the optimal solution is demanded. This is because the problems are NP-complete. This necessitates parallel heuristics/algorithms to speed-up the computation process. In this paper, we present a parallel partitioning approach for the logic optimization problem using the concept of redundancy identification. This result finds extensive applications in the area of VLSI CAD tool design.

Parallel Partitioning Techniques for Logic Minimization using Redundancy Identification

Abstract: Redundancy identification is a challenging open problem in logic optimization of Boolean circuits. Partitioning techniques are employed successfully to solve the redundancy identification problem with less time and higher scalability. Any heuristic/algorithm for the Logic optimization problem, and hence the redundancy identification problem is compute-intensive, especially when very high approximation to the optimal solution is demanded. This is because the problems are NP-complete. This necessitates parallel heuristics/algorithms to speed-up the computation process. In this paper, we present a parallel partitioning approach for the logic optimization problem using the concept of redundancy identification. This result finds extensive applications in the area of VLSI CAD tool design.

An enhanced evolutionary approach to spatial partitioning for reconfigurable environments

Abstract: This paper introduces a novel parallel evolutionary methodology making use of ANN for solving the spatial partitioning problem for multi-FPGA (field programmable gate arrays) architectures. The algorithm takes as input a HDL (hardware description language) model of the application along with user specified constraints and automatically generates a task graph G; partitions G based on the user specified constraints and maps the blocks of the partitions onto the different FPGAs in the given multi-FPGA architecture, all in a single-shot. The proposed algorithm was successfully employed to spatially partition a reasonably big cryptographic application that involved a 1024-bit modular exponentiation and to map the same onto a network of nine ACEX1K based Altera EP1K30QC208-1 FPGAs. The suggested parallel evolutionary algorithm for the partitioning step was implemented on a 6-node SGI Origin-2000 platform using the message passing interface (MPI) standard. The results obtained by executing the same are extremely encouraging, especially for larger task graphs.

Testable Clock Routing Architecture for Field Programmable Gate Arrays

Abstract: This paper describes an efficient methodology for testing dedicated clock lines in Field Programmable Gate Arrays (FPGAs). A H-tree based clocking architecture is proposed along with a test scheme. The H-tree architecture provides optimal clock skew characteristics. The H-tree architecture consumes at least 25% less of the routing resources when compared to conventional clock routing schemes. A testing scheme, which utilizes the partial reconfiguration capabilities of FPGAs through selective re-programming of the Complex Logic Blocks, to detect and locate faults in the clock lines is proposed

Testable clock routing architecture for field programmable gate arrays

Abstract: This paper describes an efficient methodology for testing dedicated clock lines in Field Programmable Gate Arrays (FPGAs). A H-tree based clocking architecture is proposed along with a test scheme. The H-tree architecture provides optimal clock skew characteristics. The H-tree architecture consumes at least 25% less of the routing resources when compared to conventional clock routing schemes. A testing scheme, which utilizes the partial reconfiguration capabilities of FPGAs through selective re-programming of the Complex Logic Blocks, to detect and locate faults in the clock lines is proposed

A Parallel Evolutionary Approach to Spatial Partitioning in Reconfigurable Environments

Abstract: This paper introduces a novel parallel methodology for solving the spatial partitioning problem for Multi-FPGA architectures. The algorithm takes as input a HDL (Hardware Description Language) model of the application along with user specified constraints and automatically generates a task graph G; partitions G based on the user specified constraints and maps the blocks of the partitions onto the different FPGAs (Field Programmable Gate Arrays) in the given Multi-FPGA architecture, all in a single-shot. The methodology suggested in this paper makes use of an evolutionary approach for the partitioning step. The proposed algorithm was successfully employed to spatially partition a reasonably big cryptographic application that involved a 1024-bit modular exponentiation and to map the same onto a network of nine ACEX1K based Altera EP1K30QC208-1 FPGAs.