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Showing papers by "V. Kamakoti published in 2004"


Proceedings ArticleDOI
05 Jan 2004
TL;DR: No Adjacent Transition (NAT) coding scheme is proposed, a bus encoding technique that simultaneously reduces power consumption and eliminates cross-talk in system-level buses.
Abstract: Considerable research has been done in the area of bus-encoding techniques, for either power minimization or cross-talk elimination in system-level buses, but not both together. We propose No Adjacent Transition (NAT) coding scheme, a bus encoding technique that simultaneously reduces power consumption and eliminates cross-talk. NAT-encoding and decoding algorithms are proposed and an analytical study of power dissipation is presented.

46 citations


Proceedings ArticleDOI
01 Dec 2004
TL;DR: By using duplication with comparison (DWC) techniques it is shown that 100% of the SEU in the LUTs can be detected for any circuit that is mapped on the proposed architecture; and for the benchmark circuits, on an average, 96%, can be automatically corrected.
Abstract: This work proposes a new CLB architecture for FPGAs that can detect and correct single event upset (SEU) faults in the LUTs. A methodology for mapping logical functions onto the LUTs is presented that exploits the features of the proposed CLB architecture to detect and correct the SEU faults in the LUTs. Experimental results obtained by mapping standard benchmark circuits on the proposed architecture indicate that on an average, 96% of the SEU in the LUTs can be detected without employing any redundancy. Further, by using duplication with comparison (DWC) techniques it is shown that 100% of the SEU in the LUTs can be detected for any circuit that is mapped on the proposed architecture; and for the benchmark circuits, on an average, 96% of the SEU in the LUTs can be automatically (without any user intervention or reconfiguration) corrected.

20 citations


Book ChapterDOI
22 Nov 2004
TL;DR: A method of face recognition using a weighted modular principle component analysis (WMPCA) has a better recognition rate, when compared with conventional PCA, for faces with large variations in expression and illumination.
Abstract: A method of face recognition using a weighted modular principle component analysis (WMPCA) is presented in this paper. The proposed methodology has a better recognition rate, when compared with conventional PCA, for faces with large variations in expression and illumination. The face is divided into horizontal sub-regions such as forehead, eyes, nose and mouth. Then each of them are separately analyzed using PCA. The final decision is taken based on a weighted sum of errors obtained from each sub-region.A method is proposed, to calculate these weights, which is based on the assumption that different regions in a face vary at different rates with expression, pose and illumination.

18 citations


Proceedings ArticleDOI
05 Jan 2004
TL;DR: The proposed architecture produces efficient solution for real-time motion estimation required in video applications with low memory bandwidth requirement and is the best tradeoff in terms of hardware overload and speed among the all-existing Three Step Search (TSS) architectures.
Abstract: This paper describes a fully pipelined parallel architecture for the New Three Step Search (NTSS) hierarchical search block-matching algorithm for the estimation of small motions in video coding. Techniques for reducing external memory accesses are also developed. The proposed architecture produces efficient solution for real-time motion estimation required in video applications with low memory bandwidth requirement. This architecture is the best tradeoff in terms of hardware overload and speed among the all-existing Three Step Search (TSS) architectures and is also suitable for estimation of small motion in video coding. This architecture can be used for various video applications from low bit-rate video to HDTV systems.

13 citations


Proceedings ArticleDOI
16 Feb 2004
TL;DR: This paper presents a methodology to utilize such unused EMBs as large look-up tables to map multi-output combinational sub-circuits of the application, which, otherwise would be mapped on to a number of small look-ups available on the FPGA.
Abstract: Modern day field programmable gate arrays (FPGA) include in addition to look-up tables, reasonably big configurable embedded memory blocks (EMB) to cater to the on-chip memory requirements of systems/applications mapped on them. While mapping applications on to such FPGAs, some of the EMBs may be left unused. This paper presents a methodology to utilize such unused EMBs as large look-up tables to map multi-output combinational sub-circuits of the application, which, otherwise would be mapped on to a number of small look-up tables (LUT) available on the FPGA. This in turn leads to a huge reduction in the area of the FPGA, utilized for mapping an application. Experimental results show that our proposed methodology, when employed on popular benchmark circuits, can lead to additional 50% reduction in area utilized when compared with other methodologies reported in the literature.

5 citations


Proceedings Article
01 Jan 2004
TL;DR: An architecture for real time face recognition using weighted modular principle component analysis (WMPCA) and a System On Programmable Chip (SOPC) implementation of face recognition system using this architecture.
Abstract: An architecture for real time face recognition using weighted modular principle component analysis (WMPCA) is presented in this paper. The WMPCA methodology splits the test face horizontally into sub-regions and analyzes each sub-region separately using PCA. The final decision is taken based on a weighted sum of the errors obtained from each region. This is based on assumption that different regions in a face vary at different rates with variations in expression and illumination. The WMPCA methodology has a better recognition rate, when compared with conventional PCA, for faces with large variations in expression and illumination. This methodology has a wide scope for parallelism. An architecture which exploits this parallelism is proposed in this paper. We also present a System On Programmable Chip (SOPC) implementation of face recognition system using this architecture.

4 citations


Proceedings ArticleDOI
06 Dec 2004
TL;DR: This work presents SHAPER, which maps the circuits onto HFPAs using reconvergence analysis and yields better area-reduction than the previous known algorithms.
Abstract: This work discusses the technology mapping problem on hybrid field programmable architectures (HFPA). HFPAs are realized using a combination of lookup tables (LUTs) and programmable logic arrays (PLAs). HFPAs provide the designers with the advantages of both LUT-based field programmable gate arrays (FPGA) and PLAs. Specifically, the use of PLAs leads to reduced area in mapping the given circuit. Designing of technology mapping methodologies which map a given circuit on to the HFPA that exploits the above-mentioned advantages is a problem of great research and commercial interest. This work presents SHAPER, which maps the circuits onto HFPAs using reconvergence analysis. Empirically, it is shown that SHAPER yields better area-reduction than the previous known algorithms.

2 citations


Proceedings ArticleDOI
22 Feb 2004
TL;DR: This paper presents the SHAPER, which maps the circuits onto HFPAs using reconvergence analysis and yields 18% better area-reduction than the previous known algorithms.
Abstract: This paper discusses the technology mapping problem on Hybrid Field Programmable Architectures (HFPA). HFPAs are realized using a combination of the following programmable logic devices, namely, Lookup Tables (LUTs) and Programmable Logic Arrays (PLAs). The HPFAs provide the designers with the advantages of both LUT-based Field Programmable Gate Arrays and PLAs. Specifically, use of PLAs can result in reduction of area required for mapping a circuit. Designing a methodology that maps a given circuit on to the HFPA that exploits the above-mentioned advantages to the maximum is a problem of very great research and commercial interest. This paper presents the SHAPER, which maps the circuits onto HFPAs using reconvergence analysis. Empirically, it is shown that SHAPER yields 18% better area-reduction than the previous known algorithms.

1 citations


Book ChapterDOI
26 Apr 2004
TL;DR: This work presents a methodology to utilize unused EMBs as large look-up tables to map multioutput combinational subcircuits of the application, with depth minimization as the main objective along with area minimization in terms of the number of LUTs used.
Abstract: Summary form only given. Modern day field programmable gate arrays (FPGA) include in addition to look-up tables, reasonably big configurable embedded memory blocks (EMB) to cater to the on-chip memory requirements of systems/applications mapped on them. While mapping applications on to such FPGAs, some of the EMBs may be left unused. We present a methodology to utilize such unused EMBs as large look-up tables to map multioutput combinational subcircuits of the application, with depth minimization as the main objective along with area minimization in terms of the number of LUTs used. Depth minimization is an important goal while mapping performance driven circuits. Experimental results show that our proposed methodology, when employed on popular benchmark circuits, leads to up to 14% reduction in depth when compared with the DAG-map algorithm, along with comparable reduction in area.

1 citations


Book ChapterDOI
22 Nov 2004
TL;DR: A new face recognition system based on eigenface analysis on segments of face images is discussed in this paper, which can tolerate local variations in the face such as expression changes and directional lighting.
Abstract: A new face recognition system based on eigenface analysis on segments of face images is discussed in this paper. The eigenfaces are extracted using principal component neural networks. The proposed recognition system can tolerate local variations in the face such as expression changes and directional lighting. Further, the system can be easily mapped onto the hardware.

1 citations


Journal Article
TL;DR: ASPIRE was successfully employed to spatially partition a reasonably big cryptographic application that involved a 1024-bit modular exponentiation and to map the same onto a network of nine ACEX1K based Altera EP1K30QC208-1 FPGAs.
Abstract: This paper introduces a CAD tool, ASPIRE (Automatic Spatial Partitioning In Reconfigurable Environments), for the spatial partitioning problem for Multi-FPGA architectures. The tool takes as input a HDL (Hardware Description Language) model of the application along with user specified constraints and automatically generates a task graph G; partitions the G based on the user specified constraints and maps the blocks of the partitions onto the different FPGAs (Field Programmable Gate Arrays) in the given Multi-FPGA architecture, all in a single-shot. ASPIRE uses an evolutionary approach for the partitioning step. ASPIRE handles the major part of the partitioning at the behavioral HDL level making it scalable with larger complex designs. ASPIRE was successfully employed to spatially partition a reasonably big cryptographic application that involved a 1024-bit modular exponentiation and to map the same onto a network of nine ACEX1K based Altera EP1K30QC208-1 FPGAs.

Book ChapterDOI
26 Apr 2004
TL;DR: ASIRE as discussed by the authors is a CAD tool for the spatial partitioning problem for multi-FPGA architectures, which takes as input a HDL (Hardware Description Language) model of the application along with user specified constraints and automatically generates a task graph G; partitions the G based on the user-specified constraints and maps the blocks of the partitions onto the different FPGAs (Field Programmable Gate Arrays).
Abstract: This paper introduces a CAD tool, ASPIRE (Automatic Spatial Partitioning In Reconfigurable Environments), for the spatial partitioning problem for Multi-FPGA architectures. The tool takes as input a HDL (Hardware Description Language) model of the application along with user specified constraints and automatically generates a task graph G; partitions the G based on the user specified constraints and maps the blocks of the partitions onto the different FPGAs (Field Programmable Gate Arrays) in the given Multi-FPGA architecture, all in a single-shot. ASPIRE uses an evolutionary approach for the partitioning step. ASPIRE handles the major part of the partitioning at the behavioral HDL level making it scalable with larger complex designs. ASPIRE was successfully employed to spatially partition a reasonably big cryptographic application that involved a 1024-bit modular exponentiation and to map the same onto a network of nine ACEX1K based Altera EP1K30QC208-1 FPGAs.