Showing papers by "V. Kamakoti published in 2012"

A buffer-sizing algorithm for network-on-chips with multiple voltage-frequency Islands

Abstract: Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect, and hence reducing them is an important problem. Application-specific designs have nonuniform network utilization, thereby requiring a buffer-sizing approach that tackles the nonuniformity. Also, congestion effects that occur during network operation need to be captured when sizing the buffers. Many NoCs are designed to operate in multiple voltage/frequency islands, with interisland communication taking place through frequency converters. To this end, we propose a two-phase algorithm to size the switch buffers in network-on-chips (NoCs) considering support for multiple-frequency islands. Our algorithm considers both the static and dynamic effects when sizing buffers. We analyze the impact of placing frequency converters (FCs) on a link, as well as pack and send units that effectively utilize network bandwidth. Experiments on many realistic system-on-Chip (SoC) benchmark show that our algorithm results in 42% reduction in amount of buffering when compared to a standard buffering approach.

ROSY: recovering processor and memory systems from hard errors

Abstract: In the nanometer era, there has been a steady decline in the semiconductor chip manufacturing yield due to various contributing factors, such as wearout and defects due to complex processes. One of the strategies to alleviate this issue is to recover and use faulty hardware at gracefully degraded performance. A common, though naive, recovery strategy followed in the context of general purpose multicore systems is to disable the cores with faults and use only the fully functional cores. Such a coarse-granular solution is suboptimal, as the disabled cores would have many working modules which go un-utilized. The Resurrecting Operating SYstem (ROSY) presented in this paper is a step towards the development of an operating system that can work on faulty cores by adapting itself to hardware faults using software workarounds, and and utilize their working components. We consider many realistic fault models and present software workarounds for them. We have developed a framework which can be trivially plugged into a fullyfeatured x86 based OS kernel to demonstrate the feasibility of the proposed ideas. Performance evaluation using SPEC benchmarks and real-world applications show that the performance degradation of the depleted cores executing ROSY is on an average between 1.6x to 4x, depending on the fault type.

Synthetic Benchmark Digital Circuits: A Survey

Abstract: Today’s VLSI CAD tools are to be designed to handle tomorrow’s designs. But, what are tomorrow’s designs? How large and complex will they be? are important questions, realistic answers for which are necessary for the tool architects. The scenario is similar in the case of hardware architects including those who design processors and FPGAs. For the VLSI CAD tool and FPGA architects, the synthetic benchmark circuits (SBCs) come to their rescue by providing representative designs of tomorrow. This paper elaborates on the various techniques reported in the literature for generation of SBCs. It also presents a case study of generating a SBC for accelerated life testing of an FPGA. The paper concludes posing interesting open issues in this field.

Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs

Abstract: System test and online test techniques are aggressively being used in today’s SoCs for improved test quality and reliability (e.g., aging/soft-error robustness). With gaining popularity of vertical integration such as 2.5D and 3D, in the semiconductor industry, ensuring thermal safety of SoCs during these test modes poses a challenge. In this paper, we propose a dynamic test scheduling mechanism for system tests and/or online test that uses dynamic feedback from on-chip thermal sensors to control temperature during shift (or scan) and capture, thereby ensuring thermal-safe conditions while applying the test patterns. The proposed technique is a closed loop test application scheme that eliminates the need for separate thermal simulation of test patterns at design stage. The technique also enables granular field-level configuration of thermal limits, so that different units across multiple cores are subjected to customized thermal profiles. Results from implementation of the proposed schemes on a 4-layer, 16-core, 12.8 million gates, OpenSparc S1 processor subsystem are presented.