V. Kamakoti

Bio: V. Kamakoti is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Field-programmable gate array & Benchmark (computing). The author has an hindex of 17, co-authored 121 publications receiving 901 citations. Previous affiliations of V. Kamakoti include National Institute of Technology, Tiruchirappalli & Indian Institute of Science.

Portable Low Cost 3 Lead Wireless Wearable ECG Device

Abstract: In this paper, we present a novel design of a portable low cost 3 Lead wireless wearable ECG device. This device acquires the raw ECG signal using three electrodes placed on the chest of the subject. An analog circuit board conditions this raw signal which is then sent to the microcontroller for further filtration of artifacts. A novel method is used for phase compensation. Bluetooth module receives the filtered data from the microcontroller and transmits it to the user’s phone where the ECG is displayed and simultaneously stored in text and JPEG format. The recorded JPEG image can be transmitted to the doctor’s mobile phone via MMS and the latter can give an instant feedback. The analog front-end (AFE) module is designed using low cost reliable components. TI’s MSP430F47186 microcontroller runs the digital filters written in C language. The Bluetooth module “WT12” is from Bluegiga and the system requires 3 volts for operation. The Android application was written in Java for acquiring, plotting and storing the data in the phone’s SD card, in text and JPEG formats. Samsung Galaxy Fit android phone was used for the prototype design. All through the system design, cost incurred was kept to a minimum.

An Architecture for Real Time Face Recognition using WMPCA

Abstract: An architecture for real time face recognition using weighted modular principle component analysis (WMPCA) is presented in this paper. The WMPCA methodology splits the test face horizontally into sub-regions and analyzes each sub-region separately using PCA. The final decision is taken based on a weighted sum of the errors obtained from each region. This is based on assumption that different regions in a face vary at different rates with variations in expression and illumination. The WMPCA methodology has a better recognition rate, when compared with conventional PCA, for faces with large variations in expression and illumination. This methodology has a wide scope for parallelism. An architecture which exploits this parallelism is proposed in this paper. We also present a System On Programmable Chip (SOPC) implementation of face recognition system using this architecture.

A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips

Abstract: Microfluidic biochips are widely accepted as the medical technology of the future. The reflection of this fact can be seen on the growth rate of the biochip industry as well. As these chips are used for many safety-critical applications, the testing and diagnosis of faults on them is of prime importance. In this paper, we present a simple approach for diagnosing faults on flow-based biochips using a two-stage search space pruning technique. The proposed technique employs a graph-theoretic bi-connected component based analysis which is much simpler and faster than those previously reported in the literature.

DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests

Abstract: At-speed testing is crucial to catch small delay defects that occur during the manufacture of high performance digital chips. Launch-Off-Capture (LOC) and Launch-Off-Shift (LOS) are two prevalently used schemes for this purpose. LOS scheme achieves higher fault coverage while consuming lesser test time over LOC scheme, but dissipates higher power during the capture phase of the at-speed test. Excessive IR-drop during capture phase on the power grid causes false delay failures leading to significant yield reduction that is unwarranted. As reported in literature, an intelligent filling of don't care bits (X-filling) in test cubes has yielded significant power reduction. Given that the tests output by automatic test pattern generation (ATPG) tools for big circuits have large number of don't care bits, the X-filling technique is very effective for them. Assuming that the design for testability (DFT) scheme preserves the state of the combinational logic between capture phases of successive patterns, this paper maps the problem of optimal X-filling for peak power minimization during LOS scheme to a variant of interval coloring problem and proposes a dynamic programming (DP) algorithm for the same along with a theoretical proof for its optimality. To the best of our knowledge, this is the first ever reported X-filling algorithm that is optimal. The proposed algorithm when experimented on ITC99 benchmarks produced peak power savings of up to 34% over the best known low power X-filling algorithm for LOS testing. Interestingly, it is observed that the power savings increase with the size of the circuit.

ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors

Abstract: With the increase in process variations and diversity in workloads, it is imperative to holistically explore optimization techniques for power and temperature from the circuit layer right up to the compiler/operating system (OS) layer. This article proposes one such holistic technique, called proactive workload aware temperature management framework for low-power chip multi-processors (ProWATCh). At the compiler level ProWATCh includes two techniques: (1) a novel compiler design for estimating the architectural parameters of a task at compile time; and (2) a model-based technique for dynamic estimation of architectural parameters at runtime. At the OS level ProWATCh integrates two techniques: (1) a workload- and temperature-aware process manager for dynamic distribution of tasks to different cores; and (2) a model predictive control-based task scheduler for generating the efficient sequence of task execution. At the circuit level ProWATCh implements either of two techniques: (1) a workload-aware voltage manager for dynamic supply and body bias voltage assignment for a given frequency in processors that support adaptive body bias (ABB); or (2) a workload-aware frequency governor for efficient assignment of upper and lower frequency bounds for frequency scaling in processors that do not support an ABB. Employing ProWATCh (with voltage manager) on an ABB-compatible 3D OpenSPARC architecture using MiBench benchmarks resulted in an average 18p (19ˆC) reduction in peak temperature. Evaluating ProWATCh on an existing quad-core Intel Corei7 processor with frequency governor alone (as the processor does not support an ABB interface) resulted in 10p (8ˆC) reduction in peak temperature when compared to what was obtained using the native Linux 3.0 completely fair scheduler (CFS). To study the effectiveness of the proposed framework across benchmark suites, ProWATCh was evaluated on a quad-core Intel Corei7 processor using CPU SPEC 2006 benchmarks which resulted in 7ˆC reduction in peak temperature as compared to the native Linux 3.0 CFS.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

A Survey of Face Recognition Techniques

Abstract: Face recognition presents a challenging problem in the field of image analysis and computer vision, and as such has received a great deal of attention over the last few years because of its many applications in various domains. Face recognition techniques can be broadly divided into three categories based on the face data acquisition methodology: methods that operate on intensity images; those that deal with video sequences; and those that require other sensory data such as 3D information or infra-red imagery. In this paper, an overview of some of the well-known methods in each of these categories is provided and some of the benefits and drawbacks of the schemes mentioned therein are examined. Furthermore, a discussion outlining the incentive for using face recognition, the applications of this technology, and some of the difficulties plaguing current systems with regard to this task has also been provided. This paper also mentions some of the most recent algorithms developed for this purpose and attempts to give an idea of the state of the art of face recognition technology.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

Abstract: High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

On-Chip Communication Architectures: System on Chip Interconnect

Abstract: Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures. KEY FEATURES * A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends * Detailed analysis of all popular standards for on-chip communication architectures * Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts * Future trends that with have a significant impact on research and design of communication architectures over the next several years