There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Face recognition presents a challenging problem in the field of image analysis and computer vision, and as such has received a great deal of attention over the last few years because of its many applications in various domains. Face recognition techniques can be broadly divided into three categories based on the face data acquisition methodology: methods that operate on intensity images; those that deal with video sequences; and those that require other sensory data such as 3D information or infra-red imagery. In this paper, an overview of some of the well-known methods in each of these categories is provided and some of the benefits and drawbacks of the schemes mentioned therein are examined. Furthermore, a discussion outlining the incentive for using face recognition, the applications of this technology, and some of the difficulties plaguing current systems with regard to this task has also been provided. This paper also mentions some of the most recent algorithms developed for this purpose and attempts to give an idea of the state of the art of face recognition technology.

https://www.koreascience.or.kr:443/article/JAKO200920237949770.pdf

A Survey of Face Recognition Techniques

High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

http://www.lcc.uma.es/~eat/pdf/itor2013.pdf

Parallel metaheuristics: recent advances and new trends

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

IR-Drop induced timing failures during testing can be avoided by minimizing the peak capturepower. This paper models the Capture-Power minimization problem as an instance of the Bottleneck Traveling Salesman Path Problem (BTSPP). The solution for the BTSPP implies an ordering on the input test vectors, which when followed during testing minimizes the Peak Capture-Power. The paper also presents a methodology for estimating a lower bound on the peak capture-power. Applying the proposed technique on ITC'99 benchmarks yielded optimal (equal to the estimated lower bound) results for all circuits. Interestingly, the technique also significantly reduced the average power consumed during testing when compared with commercial state-of-the-art tools

An efficient heuristic for peak capture power minimization during scan-based test

Interconnect Aware Test Power Reduction

Today’s VLSI CAD tools are to be designed to handle tomorrow’s designs. But, what are tomorrow’s designs? How large and complex will they be? are important questions, realistic answers for which are necessary for the tool architects. The scenario is similar in the case of hardware architects including those who design processors and FPGAs. For the VLSI CAD tool and FPGA architects, the synthetic benchmark circuits (SBCs) come to their rescue by providing representative designs of tomorrow. This paper elaborates on the various techniques reported in the literature for generation of SBCs. It also presents a case study of generating a SBC for accelerated life testing of an FPGA. The paper concludes posing interesting open issues in this field.

Synthetic Benchmark Digital Circuits: A Survey

This work discusses the technology mapping problem on hybrid field programmable architectures (HFPA). HFPAs are realized using a combination of lookup tables (LUTs) and programmable logic arrays (PLAs). HFPAs provide the designers with the advantages of both LUT-based field programmable gate arrays (FPGA) and PLAs. Specifically, the use of PLAs leads to reduced area in mapping the given circuit. Designing of technology mapping methodologies which map a given circuit on to the HFPA that exploits the above-mentioned advantages is a problem of great research and commercial interest. This work presents SHAPER, which maps the circuits onto HFPAs using reconvergence analysis. Empirically, it is shown that SHAPER yields better area-reduction than the previous known algorithms.

SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis

This paper proposes a new reconfigurable system which has a function generator-based CLB architecture. This is different from the standard look-up table (LUT) based CLB architectures available in commercial FPGAs. The new function generation architecture is based on the fact that a small set of k-input Boolean functions can generate all the 2/sup 2k/, k-input Boolean functions using a simple mapping technique. The area required by the new function generation architecture is 58.6% lesser than the area required by a standard 16/spl times/1 LUT used in commercial FPGAs. In addition, the proposed architecture consumes 40.8% lesser power than the standard 16/spl times/1 LUT. The routing architecture for the proposed reconfigurable system is the same as those present in current-day FPGAs. Hence, the algorithms presently used for technology mapping, packing, placement and routing on FPGAs can be used for the proposed reconfigurable system without much modification. The new architecture requires a 10% increase in the SRAM configuration memory. This is an insignificant penalty in comparison to the reduction in the area of the FPGA and power consumption, achieved by the proposed CLB architecture.

V. Kamakoti

Papers

An efficient heuristic for peak capture power minimization during scan-based test

Interconnect Aware Test Power Reduction

Synthetic Benchmark Digital Circuits: A Survey

SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis

A function generator-based reconfigurable system