V. Kamakoti

Bio: V. Kamakoti is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Field-programmable gate array & Benchmark (computing). The author has an hindex of 17, co-authored 121 publications receiving 901 citations. Previous affiliations of V. Kamakoti include National Institute of Technology, Tiruchirappalli & Indian Institute of Science.

Efficient Randomized Incremental Algorithm For The Closest Pair Problem Using Leafary Trees

Abstract: We present a new data structure, the Leafary tree, for designing an efficient randomized algorithm for the Closest Pair Problem. Using this data structure, we show that the Closest Pair of n points in D-dimensional space, where, D≥2, is a fixed constant, can be found in O(n log n/log log n) expected time. The algorithm does not employ hashing.

HTM design spaces: complete decoupling from caches and achieving highly concurrent transactions

Abstract: This paper proposes a Hardware Transactional Memory (HTM) design for multi-core environments. Using a novel technique to keep track of transactional read-write entries, the design provides a holistic and scalable solution to Transactional Memory (TM) implementation issues of context switching, process migration and overflow handling. Another aspect of the design is that it allows transactions to run in a highly concurrent manner by using special techniques to handle conflict resolution, conflict detection and overflows. The feasibility and validity of the proposed design are demonstrated by developing a synthesizable Hardware Description Language (HDL) model of the design and also experimenting on the same with standard benchmarks.

RaDaR: A Real-Word Dataset for AI powered Run-time Detection of Cyber-Attacks

Abstract: Artificial Intelligence techniques on malware run-time behavior have emerged as a promising tool in the arms race against sophisticated and stealthy cyber-attacks. While data of malware run-time features are critical for research and benchmark comparisons, unfortunately, there is a dearth of real-world datasets due to multiple challenges to their collection. The evasive nature of malware, its dependence on connected real-world conditions to execute, and its potential repercussions pose significant challenges for executing malware in laboratory settings. Consequently, prior open datasets rely on isolated virtual sandboxes to run malware, resulting in data that is not representative of malware behavior in the wild. This paper presents RaDaR, an open real-world dataset for run-time behavioral analysis of Windows malware. RaDaR is collected by executing malware on a real-world testbed with Internet connectivity and in a timely manner, thus providing a close-to-real-world representation of malware behavior. To enable an unbiased comparison of different solutions and foster multiple verticals in malware research, RaDaR provides a multi-perspective data collection and labeling of malware activity. The multi-perspective collection provides a comprehensive view of malware activity across the network, operating system (OS), and hardware. On the other hand, the multi-perspective labeling provides four independent perspectives to analyze the same malware, including its methodology, objective, capabilities, and the information it exfiltrates. To date, RaDaR includes 7 million network packets, 11.3 million OS system call traces, and 3.3 million hardware events of 10,434 malware samples having different methodologies (3 classes) and objectives (9 classes), spread across 30 well-known malware families.

Post-Synthesis Circuit Techniques for Runtime Leakage Reduction

Abstract: We consider the problem of reducing active mode leakage power by modifying the post-synthesis net lists of combinational logic blocks. The stacking effect is used to reduce leakage power, but instead of a separate signal one of the inputs to the gate itself is used. The approach is studied on multiplier blocks. It is found that a significant number of nets have high probabilities of being constant at 0 or 1. In specific applications such as those having high peak to average ratio, like audio and other signal processing applications, this effect is more pronounced. We show how these signals can be used to put gates to sleep, thus saving significant leakage power.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

A Survey of Face Recognition Techniques

Abstract: Face recognition presents a challenging problem in the field of image analysis and computer vision, and as such has received a great deal of attention over the last few years because of its many applications in various domains. Face recognition techniques can be broadly divided into three categories based on the face data acquisition methodology: methods that operate on intensity images; those that deal with video sequences; and those that require other sensory data such as 3D information or infra-red imagery. In this paper, an overview of some of the well-known methods in each of these categories is provided and some of the benefits and drawbacks of the schemes mentioned therein are examined. Furthermore, a discussion outlining the incentive for using face recognition, the applications of this technology, and some of the difficulties plaguing current systems with regard to this task has also been provided. This paper also mentions some of the most recent algorithms developed for this purpose and attempts to give an idea of the state of the art of face recognition technology.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

Abstract: High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

On-Chip Communication Architectures: System on Chip Interconnect

Abstract: Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures. KEY FEATURES * A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends * Detailed analysis of all popular standards for on-chip communication architectures * Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts * Future trends that with have a significant impact on research and design of communication architectures over the next several years