There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Face recognition presents a challenging problem in the field of image analysis and computer vision, and as such has received a great deal of attention over the last few years because of its many applications in various domains. Face recognition techniques can be broadly divided into three categories based on the face data acquisition methodology: methods that operate on intensity images; those that deal with video sequences; and those that require other sensory data such as 3D information or infra-red imagery. In this paper, an overview of some of the well-known methods in each of these categories is provided and some of the benefits and drawbacks of the schemes mentioned therein are examined. Furthermore, a discussion outlining the incentive for using face recognition, the applications of this technology, and some of the difficulties plaguing current systems with regard to this task has also been provided. This paper also mentions some of the most recent algorithms developed for this purpose and attempts to give an idea of the state of the art of face recognition technology.

https://www.koreascience.or.kr:443/article/JAKO200920237949770.pdf

A Survey of Face Recognition Techniques

High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

http://www.lcc.uma.es/~eat/pdf/itor2013.pdf

Parallel metaheuristics: recent advances and new trends

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

We present a simple and efficient algorithm for the nearest smallers problem (NSP) (Berkman et al., 1988) on a distributed shared memory (DSM) system with applications to problems from diverse areas. We adopt the block distributed memory (BDM) model of computation as described in (Jaja and Ryn, 1996). To the best of our knowledge this is the first known algorithm for the NSP on DSM systems. Since the NSP is fundamental in many problems, a solution for it on DSM systems implies DSM-based solutions for a variety of problems in diverse areas, as discussed in this paper. Parallel algorithms known so far for the NSP are based on shared memory systems and are therefore less scalable than our algorithm.

/pdf/an-efficient-algorithm-for-the-nearest-smallers-problem-on-48nrwe1272.pdf

An efficient algorithm for the nearest smallers problem on distributed shared memory systems with applications

In this work, we propose a novel technique for evolving transistor netlists from truth table descriptions of arbitrary digital circuits The proposed methods incorporate the effective use of genetic algorithms (GAs) In typical semi-custom and custom design flows, logic optimization is done at the gate level after Boolean translation of the input truth table The final transistor netlist is then deduced from the simplified gate logic to be laid out on a chip However transistor level optimizations after the Boolean simplification step would still not lead to the minimum number of transistors This final optimization level is non-existent in present custom design flows This work aims to address this need A salient feature of the proposed technique is the bypassing of gate level representation and optimization in the VLSI design flow We provide genetic methods to directly optimize truth table inputs using transistor level simplification This eliminates the intermediate gate level optimization step and provides optimized transistor netlists which could be used for dynamic library cell generation for custom and semi-custom designs on the fly

/pdf/a-genetic-approach-to-gateless-custom-vlsi-design-flow-3d3a7gtt8o.pdf

A genetic approach to gateless custom VLSI design flow

becomes a serious bottleneck intheexecution of programs. Resolving this contention addssignificant Thispaperlooksattwonew busarbitration overhead inmanycases. algorithms foruseinmulti-processor andmulti-core Inanybusarchitecture, abusarbitration scheme is systems, wheredifferent processors mustsharethe usedtodecide whichoftherequesting devices samebustoaccess mainmemory. These algorithms try assumesownership of thebus.Conventional toimprove uponexisting algorithms interms oflatencyarbitration schemes designed foruni-processor systems caused bycontention amongtheprocessors. Boththe donotscale well tomulti-processor systems duetothe algorithms takeintoaccountcharacteristics of contention issuedescribed above.[4]A good arbitration whicharenormally ignored, orgiven less arbitration scheme canreduce contention andimprove importance to. thethroughput oftheprocessors. [5] Thispaperpresents two new busarbitration TheRequest-Service busarbitration algorithmalgorithms, theRequest-Service algorithm andtheageattempts toremoveall formsofstarvation amongthe basedalgorithm, that havebeenparticularly designed competing processors. Arbitration takes place intwo withtheabove-mentioned issues inmind.These stages: theRequest stage, whereallrequests from algorithms are evaluated by comparing their processors arelatched ontothebus,andtheService performance withthatoftheIEEEFuturebus [1] stage, wherealltheserequests areserved. This standard. algorithm works well under conditions oflight load. A multi-core system ismodeled insoftware for simulating thevarious busarbitration algorithms. Theage-based busarbitration algorithm gives Different setsofsimulation results areobtained by morepriority toprocessors thathaverecentlyvarying theparameters ofthealgorithms, andthese acquired thebus, thusleading togreater throughput. results areanalyzed todrawaconclusion regarding the Tocontrol starvation, this scheme isusedonly aslong conditions under whichtheproposed algorithms offer asthere arefewprocessors withactive requests. This significant benefits. algorithm issuitable incases where processors haveto transfer large blocks ofdata. 2.Algorithms

https://ieeexplore.ieee.org/iel5/4799789/4808969/04809184.pdf

Studies onthePerformance ofTwoNewBusArbitration Schemes forMulti- CoreProcessors

This paper introduces a novel parallel evolutionary methodology making use of ANN for solving the spatial partitioning problem for multi-FPGA (field programmable gate arrays) architectures. The algorithm takes as input a HDL (hardware description language) model of the application along with user specified constraints and automatically generates a task graph G; partitions G based on the user specified constraints and maps the blocks of the partitions onto the different FPGAs in the given multi-FPGA architecture, all in a single-shot. The proposed algorithm was successfully employed to spatially partition a reasonably big cryptographic application that involved a 1024-bit modular exponentiation and to map the same onto a network of nine ACEX1K based Altera EP1K30QC208-1 FPGAs. The suggested parallel evolutionary algorithm for the partitioning step was implemented on a 6-node SGI Origin-2000 platform using the message passing interface (MPI) standard. The results obtained by executing the same are extremely encouraging, especially for larger task graphs.

An enhanced evolutionary approach to spatial partitioning for reconfigurable environments

This paper introduces the concept of "artificially intelligent parallel genetic algorithms", in the form of an artificial neural network, to provide a solution for the routing problem for FPGAs.

V. Kamakoti

Papers

An efficient algorithm for the nearest smallers problem on distributed shared memory systems with applications

A genetic approach to gateless custom VLSI design flow

Studies onthePerformance ofTwoNewBusArbitration Schemes forMulti- CoreProcessors

An enhanced evolutionary approach to spatial partitioning for reconfigurable environments

An artificial neural network guided parallel genetic approach to the routing problem for field programmable gate arrays