V. Nithish Kumar

Bio: V. Nithish Kumar is an academic researcher from National Institute of Technology, Tiruchirappalli. The author has contributed to research in topics: Field-programmable gate array & Cognitive radio. The author has an hindex of 4, co-authored 6 publications receiving 32 citations. Previous affiliations of V. Nithish Kumar include VIT University.

Design of area and power efficient digital FIR filter using modified MAC unit

Abstract: A novel scheme for the design of an area and power efficient digital finite impulse response (FIR) filter for digital signal processing (DSP) application's is studied in this paper. The key blocks of the filter are multipliers and adders, in which multiplier is the one which occupies the major silicon area and consumes more power. In general, the multiplication operations are performed by the shift and add logic. Most of the DSP applications demand faster adders for its arithmetic computations. Carry Select Adder (CSLA) is a well known adder for its faster computation time. Recently, an efficient Carry Select Adder (CSLA) was proposed which significantly reduce the area and power by eliminating the redundant logic gates at each bit level. In this paper, we propose an area and power efficient FIR filter implementation using modified Multiply and Accumulate (MAC) unit. The performance analysis of the proposed FIR filter is estimated with the MAC unit realized by the conventional adder and the modified carry select adder as well. The proposed FIR filter architecture with length of 5-tap and 9-tap are developed using Verilog HDL and implemented using SAED 90nm CMOS technology. The ASIC synthesis results show that the Area Delay Product(ADP) of the proposed 5-tap and 9-tap filter gains an improvement of 18.26% and 13.94%, respectively over the conventional method. Similarly, the Power Delay Product(PDP) is improved by 16.80% and 12.54%, respectively.

FPGA based decision making engine for cognitive radio using genetic algorithm

Abstract: In this paper, a novel hardware/software co-design architecture of Genetic-Algorithm (GA) driven Field Programmable Gate Array (FPGA) based decision making engine for cognitive radio is presented. Cognitive radio, which can greatly utilize the natural spectrum resource, is able to reconfigure the radio parameters according to environment change. The radio parameters defined by behavior encapsulated in the genes (frequency, modulation, power, bit error rate) of a chromosome. In our work, the modules of GA such as random number generator (RNG), Cross over, mutation are designed, synthesized using Verilog HDL. Only the fitness module implemented on NIOS processor using C. The complete design is simulated on ModelSim and implementation design targeted on ALTERA Cyclone II FPGA. By analyzing the results, the hardware/software co-design based GA yields a significant speedup over which implemented by software. This approach will attempt to increase data rate and minimize the transmission error, power consumption caused by external environment change.

Reconfigurable hybrid spectrum sensing technique for cognitive radio

Abstract: Due to massive entry of wireless services with inefficient spectrum resource utilization led to an apparent scarcity of usable radio bandwidth. Cognitive radio is well organized to utilize vacancy in the radio spectrum due to absence of primary user. Spectrum sensing i.e., detecting the presence of primary users in a licensed spectrum is the fundamental task in cognitive radio. This leads to emergence of a variety of approach to detect the presence of primary user. A two stage spectrum sensing can be used to mitigate the disadvantages of single stage detection and append the advantages of individual methods. However, the two stage detection increases the hardware and time taken to sense the spectrum. In our work, the two stage detection algorithm that was originally presented in the work of Geethu and Narayanan (2012) is efficiently implemented on Xilinx xc5vlx110t-1ff1136 FPGA using Dynamic Partial Reconfiguration (DPR) approach. The proposed architecture shows hardware improvement in terms of area and reconfiguration time over the conventional single stage detection techniques.

An efficient digital baseband encoder for short range wireless communication applications

Abstract: Various physical layer protocols are employed to encode information bits in short range wireless communication technologies. In this paper, we propose a multimode hardware architecture for a digital baseband encoder which incorporates Manchester, Differential Manchester and FM0 codes. These codes help in achieving good DC balance thereby improving signal reliability. Alternating Manchester with Differential Manchester for different intervals of time improves security at the physical layer level. This work aims at efficient integration of hardware components for the three coding modes. This hybrid architecture has a hardware utilization ratio of 100%. The design has been implemented in Xilinx Virtex 5 FPGA. This multimode encoder operates at a maximum frequency of 434 MHz. The power consumption is 34 mW at 434 MHz. When compared with the similarity-oriented logic simplification (SOLS) based integrated FM0/Manchester encoder, this encoder poses the advantage of an extra encoding operation-Differential Manchester encoding despite a slight increase in area and power.

Symbol Detection of Ambient Backscatter Systems With Manchester Coding

Abstract: Ambient backscatter communication is a newly emerged paradigm, which utilizes the ambient radio frequency signal as the carrier to reduce the system battery requirement, and is regarded as a promising solution for enabling large-scale deployment of future Internet of Things networks. The key issue of ambient backscatter communication systems is how to perform reliable detection. In this paper, we propose novel encoding methods at the information tag and devise the corresponding symbol detection methods at the reader. In particular, Manchester coding and differential Manchester coding are adopted at the information tag, and the corresponding semi-coherent Manchester (SeCoMC) and non-coherent Manchester (NoCoMC) detectors are developed. In addition, analytical bit-error-rate (BER) expressions are characterized for both detectors assuming either complex Gaussian or unknown deterministic ambient signal. Simulation results show that the BER performance of unknown deterministic ambient signal is better, and the SeCoMC detector outperforms the NoCoMC detector. Finally, compared with the prior detectors for ambient backscatter communications, the proposed detectors have the advantages of achieving superior BER performance with lower communication delay.

Design of area and power efficient digital FIR filter using modified MAC unit

Abstract: A novel scheme for the design of an area and power efficient digital finite impulse response (FIR) filter for digital signal processing (DSP) application's is studied in this paper. The key blocks of the filter are multipliers and adders, in which multiplier is the one which occupies the major silicon area and consumes more power. In general, the multiplication operations are performed by the shift and add logic. Most of the DSP applications demand faster adders for its arithmetic computations. Carry Select Adder (CSLA) is a well known adder for its faster computation time. Recently, an efficient Carry Select Adder (CSLA) was proposed which significantly reduce the area and power by eliminating the redundant logic gates at each bit level. In this paper, we propose an area and power efficient FIR filter implementation using modified Multiply and Accumulate (MAC) unit. The performance analysis of the proposed FIR filter is estimated with the MAC unit realized by the conventional adder and the modified carry select adder as well. The proposed FIR filter architecture with length of 5-tap and 9-tap are developed using Verilog HDL and implemented using SAED 90nm CMOS technology. The ASIC synthesis results show that the Area Delay Product(ADP) of the proposed 5-tap and 9-tap filter gains an improvement of 18.26% and 13.94%, respectively over the conventional method. Similarly, the Power Delay Product(PDP) is improved by 16.80% and 12.54%, respectively.