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Author

V. Ramachandran

Bio: V. Ramachandran is an academic researcher from Sir George Williams University. The author has contributed to research in topics: Transfer function & Switched capacitor. The author has an hindex of 3, co-authored 6 publications receiving 61 citations.

Papers
More filters
Book
01 Jun 1995
TL;DR: In this article, the authors present a detailed analysis of the Switched-Capacitor Ladder Filters based on Impedence Simulation and on Multiloop Feedback Concepts.
Abstract: MOS Technology and Sampled Data Filters. Analysis of Switched-Capacitor Networks. Passive Switched-Capacitor Networks. First-Order Active Switched-Capacitor Networks. Second-Order Active SC Filters. Switched-Capacitor Ladder Filters Based on Impedence Simulation. SC Filters Based on Operational Simulation of LC Ladders and on Multiloop Feedback Concepts. Switched-Capacitor N-Path Filters. Practical Considerations in the Design of Switched-Capacitor Networks and Their Applications. Appendices.

47 citations

Journal ArticleDOI
TL;DR: A general first-order switched-capacitor network using one operational amplifier, insensitive to stray capacitances, is proposed and its application to realise an inverting bilinear lossy integrator and a circuit for realising finite zeros is discussed.
Abstract: A general first-order switched-capacitor network using one operational amplifier, insensitive to stray capacitances, is proposed. Its application to realise an inverting bilinear lossy integrator and a circuit for realising finite zeros is discussed.

12 citations

Journal ArticleDOI
TL;DR: In this paper, a procedure for realising unsymmetrical lattice structures using polynomial-decomposition techniques is presented, which realises any nth-order 2-element-kind voltage or current transfer function with maximum gain and minimum number of elements.
Abstract: The letter presents a procedure for realising unsymmetrical lattice structures using polynomial-decomposition techniques. This realises any nth-order 2-element-kind voltage or current transfer function with maximum gain and minimum number of elements. Only RC voltage transfer functions are considered.

3 citations

01 Jan 1983
TL;DR: In this paper, a set of formulas for computing the maximum magnitude of a seeond-order digital transfer function is presented for switching-capacitor (SC) filters with optimal dynamic range.
Abstract: AMract-Formulas for evaluating the maximum magnitude of a seeond-order digital transfer function are given. These are especially useful for designing switched-capacitor (SC) filters with optimal dynamic range. It is known that switched-capacitor (SC) filters using one (or two) operational amplifiers can have two (or even four) different transfer functions. Dynamic range optimization necessitates firstly, evaluation of the maximum magnitudes of all these transfer functions over certain frequency range using some computeraided-analysis program and then scaling the capacitor values to equalize the maxima thus obtained. Since one is interested in the maxima of the transfer functions only, we present herein a set of formulas for quick computation of these maxima. The results presented are believed to be useful in general, in discrete-time filter design. Considering a general second-order digital transfer function
Journal ArticleDOI
TL;DR: In this article, a nonsymmetrical lattice in which all coils can be made lossy is given, and a method for realising a v.t.f. by nonsymmetric lattices is given.
Abstract: A method for realising a v.t.f.by a nonsymmetrical lattice in which all coils can be made lossy is given.

Cited by
More filters
Journal ArticleDOI
TL;DR: A design methodology for synthesis of active N-path bandpass filters is introduced and a 0.1-to-1.2 GHz tunable 6th-order N- path channel-select filter in 65 nm LP CMOS is introduced, achieving a “flat” passband shape and high out-of-band linearity.
Abstract: A design methodology for synthesis of active N-path bandpass filters is introduced. Based on this methodology, a 0.1-to-1.2 GHz tunable 6th-order N-path channel-select filter in 65 nm LP CMOS is introduced. It is based on coupling N-path filters with gyrators, achieving a “flat” passband shape and high out-of-band linearity. A Miller compensation method is utilized to considerably improve the passband shape of the filter. The filter has 2.8 dB NF, +25 dB gain, +26 dBm wideband IIP3 ( MHz), an out-of-band 1 dB blocker compression point B1dB,CP of +7 dBm (Δf = +50 MHz) and 59 dB stopband rejection. The analog and digital part of the filter draw 11.7 mA and 3-36 mA from 1.2 V, respectively. The LO leakage to the input port of the filter is ≤-64 dBm at a clock frequency of 1 GHz. The proposed filter only consists of inverters, switches and capacitors and therefore it is friendly with process scaling.

156 citations

Journal ArticleDOI
TL;DR: A widely tunable 4th order BPF based on the subtraction of two 2nd order 4-path passive-mixer filters with slightly different center frequencies is proposed.
Abstract: A widely tunable 4th order BPF based on the subtraction of two 2nd order 4-path passive-mixer filters with slightly different center frequencies is proposed. The center frequency of each 4-path filter is slightly shifted relative to its clock frequency (one upward and the other one downward) by agm-C technique. Capacitive splitting of the input signal is used to reduce the mutual loading of the two 4-path BPFs and increase their quality factors. The filter is tunable from 0.4 GHz to 1.2 GHz with approximately constant bandwidth of 21 MHz. The in-band 1-dB compression point of the filter is -4.4 dBm while the in-band IIP3 of the filter is +9 dBm and the out-of-band IIP3 is + 29 dBm (Δf=+50 MHz). The ultimate rejection of the filter is >; 55 dB and the NF of the filter is 10 dB. The static and dynamic current consumption of the filter are 2.8 mA from 2.5 V and 12 mA from 1.2 V, respectively (at 1 GHz). The LO leakage power to the input port is <; - 60 dBm. The filter has been fabricated in CMOS LP 65 nm technology and the active area is 0.127 mm2.

131 citations

Patent
15 Oct 1987
TL;DR: In this paper, a switched-capacitor filter constituted in the form of a semiconductor integrated circuit has an input circuit which consists of at least one non-inversion-type switch and at least two inversion type switch.
Abstract: A switched-capacitor filter constituted in the form of a semiconductor integrated circuit has an input circuit which consists of at least one noninversion-type switched-capacitor and at least two inversion-type switched-capacitors that are connected in parallel with each other. The two inversion-type switched-capacitors have different writing timings and reading timings relative to each other. With this setup, capacitances of the switched-capacitors need not be extremely increased even when it is desired to maintain a zero-point frequency of the filter at a very low value. Further, there is no need of providing a circuit such as sample holding circuit which requires extra area and consumes additional electric power.

69 citations

Journal ArticleDOI
TL;DR: This work analyzes several examples of switched linear circuits and a switched spring-mass system to illustrate the physical manifestations of regressivity and nonregressivity for discrete and continuous time systems as well as hybrid discrete/continuous systems from a time scales perspective.

53 citations

Journal ArticleDOI
TL;DR: Switched-capacitor fractional-step filter design of low-pass filter prototypes with Butterworth characteristics is reported for the first time using discrete-time integrators which implement both the bilinear and the Al-Alaoui s-to-z transformations.
Abstract: Switched-capacitor fractional-step filter design of low-pass filter prototypes with Butterworth characteristics is reported in this work for the first time. This is achieved using discrete-time integrators which implement both the bilinear and the Al-Alaoui s-to-z transformations. Filters of orders 1.2, 1.5 and 1.8 as well as 3.2, 3.5, and 3.8 are designed and verified using transistor-level simulations with Cadence on AMS $$0.35\,\upmu $$0.35μm CMOS process. Digital programmability of the fractional-step filters is also achieved.

39 citations