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V. Ravi

Bio: V. Ravi is an academic researcher from VIT University. The author has contributed to research in topics: Memristor & Static random-access memory. The author has an hindex of 6, co-authored 22 publications receiving 73 citations.

Papers
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Journal ArticleDOI
TL;DR: The proposed write scheme under various memristor faults is found to enhancing the reliability of memristors efficiently and is validated by means of Monte-Carlo analysis by infusing the random variations of internal parameters of Memristor as well.
Abstract: The non-deterministic nature of memristor and its unreliable behavior are the two major concerns hampering its growth and industrial manufacturability. The endurance and reliability of memristor memories are affected not only by the process variations (intrinsic), but also due to the electrical stress created by interfacing peripheral circuits (extrinsic). Concerning the intrinsic faults in transition metal oxide (TMO) memristors, drifting of oxygen vacancies across the device is responsible for SET/RESET operation. It is likely that such drifting might induce switching faults during the device operation, for instance endurance of the memory. Thus, the application of a fixed write pulse may not suffice to achieve successful write operations under these circumstances. To circumvent the above pitfall, we propose here a new technique by designing a fault tolerant adaptable write scheme which can adapt by itself based on the behavior and switching faults. Accordingly, the proposed write scheme identifies the optimal amplitude and the width for write pulse. The proposed write scheme under various memristor faults is found to enhancing the reliability of memristors efficiently. Further, the results are validated by means of Monte-Carlo analysis by infusing the random variations of internal parameters of memristors as well.

12 citations

Journal ArticleDOI
TL;DR: The proposed Built-In-Self-Test (BIST) using self-checking circuits for bit array multipliers forms the base of area and power efficient testing methodologies for digital circuits.
Abstract: Background: Current technologies results in gradual increase in sensitiveness towards faults causing malfunctioning of the circuit. This paper presents the novel design of Built-In-Self-Test (BIST) using self-checking circuits for bit array multipliers. Methods: The design of BIST comprises of self-checking full adder which ensures fault detection on the same chip area. Each regular full adders and half adders in bit array multipliers are replaced by self-checking full adder so that any transient or permanent faults can be detected and recovered. The proposed BIST design also allows power saving procedures in Power Efficient-Test Pattern Generator (PE-TPG). Findings: Simulation results shows that implementation of this self-checking full adder into standard bit array multiplier minimizes the area overhead and power consumption by 25%-30% as compared to previous self-checking designs. The proposed BIST can handle up to ten faults with 70% probability of error detection, which is higher than earlier Double Modular Redundancy (DMR) as well as Triple Modular Redundancy (TMR) technique with handling of six faults with 60% error detection probability. Conclusion: The proposed BIST design forms the base of area and power efficient testing methodologies for digital circuits. The architecture of BIST can be modified according to the data path of multiplier under test.

11 citations

Journal ArticleDOI
TL;DR: This proposed scheme becomes more efficient by using cellular automata as test pattern generation and response analyzer using rule 90 to test the circuit under test in online mode with less concurrent test latency and less area overhead.
Abstract: Background/objectives: Built in Self Test Architectures are used for the online or offline testing of the digital circuits and can be operated both in normal as well as test mode. So the objective is to test the circuit under test in online mode with less concurrent test latency and less area overhead. Methods/ Statistical Analysis: In the case of normal mode the time required for testing becomes undesirable parameter so here we prefer offline testing method with concurrent approach which is also monitoring the window at the input by applying input vectors considering circuit under test as most important part of the processor which is arithmetic logic unit. Findings: The particular locations of the input vectors are stored in the latches which worked as the memory elements and this proposed scheme becomes more efficient by using cellular automata as test pattern generation and response analyzer using rule 90. Application/Improvement: The proposed scheme is comparable with the same architecture, considering TPG as LFSR (Linear Feedback Shift Register) and counter.

9 citations

Journal ArticleDOI
Neha Sinha1, V. Ravi1
TL;DR: A realistic design model of health monitoring system is implemented which can be used for future hardware design and it is proved that realistic design is possible for future health care system design.
Abstract: Background: Research shows that the health care cost per capita have grown 2.4 percent faster than the gross domestic product (GDP) since 1970. The aim of this paper is to present a useful model of wireless system that can combine both hardware and software environments and it can also integrate with other technologies or infrastructure at a low cost, which can be used for the patient monitoring system. Methods: The biomedical sensor which is attached to the patient, will read analog data. The recorded data will be converted digitally by using Analog to Digital Converter (ADC) and a FPGA transmitter will be used to send this data to Phase Shift Keying (PSK) transmitter. The modulated data will be received by PSK receiver and another FPGA receiver will be used to get the data back on the system. For behavioural modelling Verilog hardware descriptive language is used to provide a high level abstraction and language constructions. And the Simulink software is used to provide a high-level mathematical modelling condition for digital communication system which can be used for the verification and algorithm development.The important modules implemented for the transmitter and receiver FPGA are bus interfacing, compression and the data framing. Findings: A short range wireless health monitoring wireless system is modelled by using a mixed software and hardware simulation environment.At all the stages of the hardware and software designs, different types of languages like Verilog HDL codes and MATLAB used to verify the operation of the modules. The behavioural HDL designed of the FPGA transmitter and receiver will be interfaced with the RF Simulink models of PSK transmitter and receiver by using System Generator (Sysgen) tool that acts as the converter simulator. A realistic design model of health monitoring system is implemented which can be used for future hardware design. Compression and framing are the two main operations used in the transmitter side. Data compression is implemented by Run-Length Encoding method and for data framing high data link control protocol has been used. The unique features of this models simulation are low cost, less complexity, low power dissipation and efficient data transmission. Finally the FPGA based healthcare system allows us to change the design configurations or up gradation of the system based on the requirements. Conclusion: In this paper distributed simulation approach is used for designing the health monitoring system which allows checking the specification of design at all the stages. Simulation by HDL and Simulink mixed models in not the objective of this work, but to prove that realistic design is possible for future health care system design.

9 citations


Cited by
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Journal ArticleDOI
TL;DR: An associative memory, designed and simulated using the spin-based synapse, performs very similar to its ideal software-based counterpart, with about 8% difference in successful recall rate.
Abstract: Bio-inspired computing attempts to emulate the computations performed by biological neural networks, like those in the human brain, to benefit from efficiencies in flexibility, parallel processing, and, most importantly, learning. We simulate a fully nonvolatile spin-based synapse utilizing a magnetic tunnel junction (MTJ) and a neuron based on a carbon nanotube field-effect transistor (CNTFET). The modeled synapse benefits from the features of MTJs like nonvolatility, high endurance, and reconfigurability. The features of CNTFETs are utilized to streamline the design. The functionality and characteristics of the synapse in the inevitable presence of process variations are validated using Monte Carlo simulations. An associative memory, designed and simulated using the spin-based synapse, performs very similar to its ideal software-based counterpart, with about 8% difference in successful recall rate.

29 citations

Journal ArticleDOI
TL;DR: In this article, the retention time and endurance of memristor RRAM memory elements based on reversible resistive switching in oxide dielectrics are studied, and the influence of external parameters (switching pulses and ambient temperature) as well as internal factors (evolution of the concentration of oxygen vacancies in the filament region, the material, structure; the thickness of the active dielectric layer, material of metal electrodes on the long-term stability of high resistance state (HRS) and the low resistance states (LRS) of the memristors) is discussed.
Abstract: In this review of experimental studies, the retention time and endurance of memristor RRAM memory elements based on reversible resistive switching in oxide dielectrics are studied. The influence of external parameters—switching pulses and ambient temperature—as well as internal factors—evolution of the concentration of oxygen vacancies in the filament region, the material, structure; the thickness of the active dielectric layer, material of metal electrodes on the long-term stability of high resistance state (HRS) and the low resistance state (LRS) of the memristor is discussed.

18 citations

Journal ArticleDOI
01 Jan 2021
TL;DR: The characteristics, applications, progress, and challenges of memristors in hardware security are examined and the benefits and limitations of different schemes as accelerators for hardware information protection are compared.
Abstract: Memristors are widely used in hardware security applications. Research progress in memristor‐based physical unclonable functions (PUFs), random number generators (RNGs), and chaotic circuits is reviewed. To enhance device security, PUFs and RNGs apply randomness of memristors and incorporate 3D crossbars to amplify the number of challenge‐response pairs and provide proof of the destruction of the key, which enables the administrator to firmly control the device information. In addition, the image encryption technique based on the chaotic system is summarized. Furthermore, an assessment of the research advancement in PUFs, RNGs, and chaotic circuits is conducted. This Review examines the characteristics, applications, progress, and challenges of memristors in hardware security and compares the benefits and limitations of different schemes as accelerators for hardware information protection.

16 citations

Journal ArticleDOI
TL;DR: The proposed write scheme under various memristor faults is found to enhancing the reliability of memristors efficiently and is validated by means of Monte-Carlo analysis by infusing the random variations of internal parameters of Memristor as well.
Abstract: The non-deterministic nature of memristor and its unreliable behavior are the two major concerns hampering its growth and industrial manufacturability. The endurance and reliability of memristor memories are affected not only by the process variations (intrinsic), but also due to the electrical stress created by interfacing peripheral circuits (extrinsic). Concerning the intrinsic faults in transition metal oxide (TMO) memristors, drifting of oxygen vacancies across the device is responsible for SET/RESET operation. It is likely that such drifting might induce switching faults during the device operation, for instance endurance of the memory. Thus, the application of a fixed write pulse may not suffice to achieve successful write operations under these circumstances. To circumvent the above pitfall, we propose here a new technique by designing a fault tolerant adaptable write scheme which can adapt by itself based on the behavior and switching faults. Accordingly, the proposed write scheme identifies the optimal amplitude and the width for write pulse. The proposed write scheme under various memristor faults is found to enhancing the reliability of memristors efficiently. Further, the results are validated by means of Monte-Carlo analysis by infusing the random variations of internal parameters of memristors as well.

12 citations