Vaithiyanathan Dhandapani

Bio: Vaithiyanathan Dhandapani is an academic researcher from National Institute of Technology Delhi. The author has contributed to research in topics: Deep learning & Brightness. The author has an hindex of 1, co-authored 7 publications receiving 2 citations.

Approximate Multipliers Using Bio-Inspired Algorithm

Abstract: As most of the real-world problems are imprecise, dedicating a lot of hardware for precise computations is futile for low-power applications and few applications where the precision is not of paramount importance. For such applications an imprecise computational block is sufficient if it has other performance benefits like low power and low area. We propose Constrained Cartesian Genetic Programming (CCGP), a variant of CGP to evolve lower order imprecise multipliers and further the higher order multipliers are constructed from them. Gate-level architectures for 2 × 2, 3 × 2, 3 × 3 and 4 × 4 imprecise multipliers are evolved. Also, we propose few partitioning methodologies for the construction of higher order multipliers using the evolved imprecise lower order multipliers. The constructed evolved-partitioned multiplier (EPM) of orders 8 × 8 and 16 × 16 has significant performance benefits over the existing multiplier architectures in terms of cell area and power. The circuits are synthesized using Cadence SoC Encounter® using TSMC® 180 nm standard cell library. The 16-bit EPMs show a maximum power reduction of 33% compared to other truncated multipliers and an area improvement of 2%.

Decisive structures for multirate FIR filter incorporating retiming and pipelining schemes

Abstract: Purpose Very large-scale integration (VLSI) digital signal processing became very popular and is predominantly used in several emerging applications. The optimal design of multirate filter with improvement in performance parameters such as less area, high speed and less power is the challenging task in most of the signal processing applications. This study aims to propose several effective multirate filter structures to accomplish sampling rate conversion. Design/methodology/approach The multirate filter structures considered in this work are polyphase filter and coefficient symmetry-based finite impulse response filter. The symmetry scheme particularly brings down the complexity to significant extent. To bring improvement in speed, delay registers are inserted at appropriate path with the help of pipelining and retiming scheme. Findings In this paper, the three tasks have been considered. First, the polyphase coefficient symmetry and modified polyphase (MP) structure is designed. Second, the pipelining is applied to the polyphase structure and the obtained results are compared with the polyphase structure. In third, retiming is applied to the polyphase structure and the performance comparison is carried out. The structures are realized for various orders, and the comparative analysis is carried out with the filter order N = 12, 30, 42, 8, 11 and 24 and the results are stated. The performance of all the accomplished structures is analyzed using Altera Quartus with the family cyclone II, device EP2C70F672C6. The results show that the multirate filter using pipelining and retiming offers better performance when examining with the conventional structures. Retimed and pipelined MP structure achieves a speed enhancement of about 33.81% when examining with the conventional polyphase (CP) structure with retiming and pipelining for N = 24 and M = 5. Likewise, the 2/3 structure of pipelined coefficient symmetry approach offers area reduction of about 54.76% over 2/3 structure of pipelined polyphase approach for N = 30 with little reduction in power. The fine grain pipelined and retimed MP structure with N = 11 and M = 3 avails critical path delay reduction of about 28.15% when examining with the corresponding fine grain pipelined and retimed CP structure. Originality/value The proposed distinct structures offer better alternative to conventional structures because of the symmetric coefficients, performance enhancement using pipelining and retiming based rate conversion structures. The suggested structures can be used for achieving different rates in software radios.

Implementation of Attendance Management System Based on Text and Face Recognition

Abstract: In this paper, the attendance management system is implemented for replacing the existing marking system, which is practiced manually. To achieve this, text recognition is used to scan the identity (ID) card and analyse it; furthermore, facial recognition is used based on demand. The ID card is scanned and by text recognition and verifies the student’s details with the database of registered students. Moreover, to avoid proxy in attendance, it also captures the image of the person handling and the image present in the database. For text recognition, the cloud services named Nanonets were adopted. For face recognition, the popular cloud services like Amazon web services (AWS) were adopted to create an application program interface (API) request. However, before sending this image to one of the cloud services for analysing and identifying the faces, initially, it uses open-source computer vision (OpenCV), a library of programming functions for image processing and to detect if a face is present in a given image database or not.

An Optimized FPGA Architecture for Sleep Level Categorization Using Fuzzed Utilized Machine Learning Approach

Abstract: In this chapter, an efficient FPGA architecture is proposed to categorize and analyze the sleep level. This proposed architecture is implemented using four sub parts which are namely preprocessing unit, FIR filtering, self-regulated learning, and fuzzy deduction. The EEG (electro encephalo gram) and EMG (electro myogram) are signal samples are considered for the analysis of this sleep level. The signals are initially preprocessed to remove undesired signal components. Further, a reconfigurable multichannel multiply accumulate (MAC)-based FIR filter is utilized for achieving the desired signal. Then the signal is classified based on the reference data with the use of self-regulated machine learning and fuzzy deduction schemes which involves averaging and thresholding process. Further, the signals are categorized into completely awake level, partially awake level, and sleep level using fuzzy if-then rules. The performance parameters are analyzed in terms of sensitivity, specificity, latency, area occupied, power consumption, and speed enhancement.

Underwater Image Enhancement via Adaptive Group Attention-Based Multiscale Cascade Transformer

Abstract: The absorption and scattering caused by the underwater medium degrade the quality of underwater optical imaging, which limits the further development of underwater tasks. Recently, transformer-based methods have shown the same excellent performance as convolutional neural networks (CNNs) in various vision tasks, but the huge parameters of such networks hinder their application deployment. In this article, we propose novel adaptive group attention (AGA), which can dynamically select visually complementary channels based on the dependencies, reducing the number of further attention parameters. The AGA is applied in the Swin Transformer module and used to design an end-to-end underwater image enhancement network. The network also introduces the multiscale cascade module and the channel attention mechanism. This article conducted ablation study and qualitative and quantitative comparisons on public datasets, and the results show that the application of AGA significantly compresses the model size while ensuring performance, and other application components have the significant gain on the network. Compared with other advanced methods, the network in this article has outstanding performance.

An intelligent bike safety and surveillance system

Abstract: Now a day's usage of Two-wheeler is exponentially increasing and the accidents met by them also increases every year. Even though the Safety precautions and traffic rules are there the riders are not showing interest in following the safety measures and rules. An intelligent Bike Safety and Surveillance (IBSS) is a real time system which makes a rider to follow safety measures and the rules. The System Comprise of Helmet unit & Vehicle unit with antitheft and Speed Control mode. The helmet unit ensures whether the Rider is wearing a helmet, Alcohol Consumption of the rider and the proper release of Side stand. The Vehicle unit Comprises of the Surveillance system which check and intimate if an Accident is occurred. The antitheft mode protects the vehicle from unauthorized users. The Speed control mode monitors the speed and automatically control the speed of the Vehicle. The System is implemented using Arduino UNO and ATmega 328 Microcontroller with different sensors.