This paper discusses in detail the effects of Sub-10nm fin-width ( $\text{W}_{fin}$ ) on the analog performance and variability of FinFETs. It is observed through detailed measurements that the trans-conductance degrades and output conductance improves with the reduction in fin-width. Through different analog performance metrics, it is shown that analog circuit performance, in Sub-10nm $\text{W}_{fin}$ regime, cannot be improved just by $\text{W}_{fin}$ scaling but by optimizing source/drain resistance, gate dielectric thickness together with the $\text{W}_{fin}$ scaling. We also explored the effect of process induced total and random variability on trans-conductance and output conductance of FinFETs. A systematic strategy to decouple different variability sources has been discussed and it is shown that mobility, source/drain resistance and oxide thickness are the critical parameters to reduce variability.

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Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis

Selective epitaxial growth of high-P Si:P for dource/drain formation in advanced Si nFETs

This work experimentally investigates the effect of fm-width $(W_{fin})$ scaling in sub-10nm regime on the analog performance of nFinFETs. It is shown that the device trans-conductance $(g_{m})$ degrades and output conductance $(g_{ds})$ improves with reduction in $W_{fin}.$ Various sources affecting the variability of $g_{m}$ and gds in sub-10nm $W_{fin}$ regime are also explored. Through different analog performance metrics, it is shown that the analog performance of thinner fin FinFETs can be further increased by properly optimizing the S/D resistance and gate dielectric.

Effect of Sub-10nm Fin-widths on the Analog Performance of FinFETs

Two-dimensional (2D) van der Waals semiconductors are appealing for low-power transistors. Here, we show the feasibility in enhancing carrier mobility in 2D semiconductors through engineering the vertical distribution of carriers confined inside the ultrathin channels via symmetrizing gate configuration or increasing channel thickness. Through self-consistently solving the Schr\"odinger-Poisson equations, the shapes of electron envelope functions are extensively investigated by clarifying their relationship with gate configuration, channel thickness, dielectric permittivity, and electron density. The impacts of electron distribution variation on various carrier scattering matrix elements and overall carrier mobility are insightfully clarified. It is found that the carrier mobility can be generally enhanced in the dual-gated configuration due to the centralization of carrier redistribution in the nanometer-thick semiconductor channels and the rate of increase reaches up to 23% in HfO$_2$ dual-gated 10-layer MoS$_2$ channels. This finding represents a viable strategy for performance optimization in transistors consisting of 2D semiconductors. 

Enhancement of Carrier Mobility in Semiconductor Nanostructures by Carrier Distribution Engineering

The low-frequency (LF) noise characterization of Si0.7Ge0.3 pFinFETs and transistors’ performance were analyzed for different NH3 post deposition annealing (PDA) temperatures. The flicker noise of these pFinFETs is dominated by carrier number fluctuations at low and intermediate drain currents. At high gate overdrive, the voltage noise <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${S}_{\text {vg}}$ </tex-math></inline-formula> increases dramatically and the effect of the access resistance cannot be ignored. By analyzing the input-referred voltage noise power spectral density(PSD) at flat band voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${S}_{\text {vgfb}}$ </tex-math></inline-formula> ), we will demonstrate that nitridation of the high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> layer at 650 °C yields the best quality gate-stack and also results in the highest mobility. While NH3 PDA temperature above 650 °C may introduce more hydrogen at the oxide layer and at the interface, hydrogen can induce hole traps and interface traps that degrade the quality of the gate-stack and reduce the mobility. 

Valentina Terzeiva

Papers

Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis

Effect of Sub-10nm Fin-widths on the Analog Performance of FinFETs