Valipe Ramgopal Rao

TL;DR: In this paper, the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions was studied and the use of high-kappa spacers to enhance the effect of GFIBL and thereby achieve better device and circuit performance.

TL;DR: In this article, the effects of halo [both double-halo (DH) and single-Halo or lateral asymmetric channel (LAC)] doping on the sub-threshold analog performance of 100-nm CMOS devices are systematically investigated for the first time with extensive process and device simulations.

TL;DR: In this article, the potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K/sub gate/) using two-dimensional (2-D) device and Monte Carlo simulations.

TL;DR: In this article, a detailed physical insight on the lattice heating and heat flux in a 3D front end of the line and complex back end of line of a logic circuit network is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD.

TL;DR: In this paper, a physics-based dc compact model for SOI tunnel field effect transistors (TFETs) was developed utilizing Landauer approach, and the important transistor electrical parameters, such as threshold voltage Vth, charge in the channel Q, gate capacitance CG, drain current IDS, subthreshold swing S, transconductance gm, and output conductance gDS, have been modeled.