Veit B. Kleeberger

Bio: Veit B. Kleeberger is an academic researcher from Infineon Technologies. The author has contributed to research in topics: Fault injection & Resilience (network). The author has an hindex of 10, co-authored 30 publications receiving 291 citations. Previous affiliations of Veit B. Kleeberger include Technische Universität München.

Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies

Abstract: With continued scaling of CMOS technology it becomes increasingly difficult to maintain reliable circuits. Early predictive technology and design exploration help to understand major effects of variability sources and their impact on circuit performances. With each new technology basic circuit blocks have to be redesigned to appropriately evaluate the impact of technology scaling. Therefore, this paper presents an approach which is able to find the optimal sizing of basic circuit blocks considering process variation. We utilize this approach to predict the impact of scaling in FinFET technologies and the influence of process variations in future technology nodes.

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience

Abstract: Highly scaled technologies at and beyond the 22-nm node exhibit increased sensitivity to various scaling-related problems that conspire to reduce the overall reliability of integrated circuits and systems. In prior technology nodes, the assumption was that manufacturing technology was responsible for ensuring device reliability. This basic assumption is no longer tenable. Trying to contain reliability problems purely at the technology level would cause prohibitive increases in power consumption. Thus, a cross-layer approach is required, which spreads the burden of ensuring resilience across multiple levels of the design hierarchy. This article illustrates a methodology for dealing with scaling-related problems via two case studies that link models of low-level technology-related problems to system behavior.

Workload- and Instruction-Aware Timing Analysis: The missing Link between Technology and System-level Resilience

Abstract: In today's design of resilient embedded systems, logic circuit components play a key role. Many possible design choices at the gate level, such as implementation architecture or synthesis constraints, are vital for the resilience of the entire system. Hence, EDA algorithms at this level have to support exposing technology characteristics (such as process variations or aging) for consideration on higher levels of abstraction. Similarly, key parameters from system level, such as workload or executed processor instructions, have to be considered at lower levels for accurate analysis of, e.g., degradation effects. Circuit-level timing analysis plays a key role in this context as it provides key metrics such as achievable frequency, available timing margins and timing violation vulnerabilities of the analyzed circuit. We present an enhanced static timing analysis which links technology-level effects to system-level and vice versa. Specifically, we discuss the accurate and efficient consideration of system workload and impact of executed instructions on circuit timing.

Addressing failures in exascale computing

Abstract: We present here a report produced by a workshop on 'Addressing failures in exascale computing' held in Park City, Utah, 4-11 August 2012. The charter of this workshop was to establish a common taxonomy about resilience across all the levels in a computing system, discuss existing knowledge on resilience across the various hardware and software layers of an exascale system, and build on those results, examining potential solutions from both a hardware and software perspective and focusing on a combined approach. The workshop brought together participants with expertise in applications, system software, and hardware; they came from industry, government, and academia, and their interests ranged from theory to implementation. The combination allowed broad and comprehensive discussions and led to this document, which summarizes and builds on those discussions.

Reliable on-chip systems in the nano-era: lessons learnt and future trends

Abstract: Reliability concerns due to technology scaling have been a major focus of researchers and designers for several technology nodes. Therefore, many new techniques for enhancing and optimizing reliability have emerged particularly within the last five to ten years. This perspective paper introduces the most prominent reliability concerns from today's points of view and roughly recapitulates the progress in the community so far. The focus of this paper is on perspective trends from the industrial as well as academic points of view that suggest a way for coping with reliability challenges in upcoming technology nodes.

Design and architectures for dependable embedded systems

Abstract: The paper presents an overview of a major research project on dependable embedded systems that has started in Fall 2010 and is running for a projected duration of six years. Aim is a ‘dependability co-design’ that spans various levels of abstraction in the design process of embedded systems starting from gate level through operating system, applications software to system architecture. In addition, we present a new classification on faults, errors, and failures.

Toward Smart Embedded Systems: A Self-aware System-on-Chip (SoC) Perspective

Abstract: Embedded systems must address a multitude of potentially conflicting design constraints such as resiliency, energy, heat, cost, performance, security, etc., all in the face of highly dynamic operational behaviors and environmental conditions. By incorporating elements of intelligence, the hope is that the resulting “smart” embedded systems will function correctly and within desired constraints in spite of highly dynamic changes in the applications and the environment, as well as in the underlying software/hardware platforms. Since terms related to “smartness” (e.g., self-awareness, self-adaptivity, and autonomy) have been used loosely in many software and hardware computing contexts, we first present a taxonomy of “self-x” terms and use this taxonomy to relate major “smart” software and hardware computing efforts. A major attribute for smart embedded systems is the notion of self-awareness that enables an embedded system to monitor its own state and behavior, as well as the external environment, so as to adapt intelligently. Toward this end, we use a System-on-Chip perspective to show how the CyberPhysical System-on-Chip (CPSoC) exemplar platform achieves self-awareness through a combination of cross-layer sensing, actuation, self-aware adaptations, and online learning. We conclude with some thoughts on open challenges and research directions.